Circuitgraph

Fixed
- Approximate model counting subprocess newlines and encoding
- `set_type` docstring
- `props.influence` docstring
- Ternary transform for circuits with xor/xnor gates
- `sat.construct_solver` works with newer versions of `python-sat`

Added
- Generic flop blackbox
- `insert_registers` transform
- `limit_fanout` transform
- `levelize` function

Changed
- `sat.construct_solver` accepts a `pysat.Solver` class instead of a string for greater flexibility. If no solver is specified, `Cadical` (`Cadical153` for newer versions of `python-sat`) will be used.
- Added `stretch` argument to Yosys `show` command for `cg.visualize`

Fixed
- Visualization with BlackBoxes.

Added
- Supergate construction functionality.

Changed
- `output` is no longer a node type but an extra property. It can be accessed using `Circuit.is_output` and `Circuit.set_output`. Any node with a primitive gate type can also be marked as an output.
- Import structure has changed. Most functions should now be referrenced based on their parent module, e.g., `cg.tx.syn` instead of `cg.syn`.
- Most module names have been shortened for ease of use with new import structure.
- Renamed `sat` function to `solve`.
- Removed `copy` from `tx`. Copying a circuit can be done using `Circuit.copy`.

Added
- More robust checks for incorrect circuit construction
- More robust parsing, including faster parsing using regex
- Simple circuit visualization
- `x` type for nodes (similar to `0`, and `1`)
- Sequential unroll transform

Fixed
- Synthesis now works with python3.6 again

Added
- DesignCompiler synthesis

Fixed
- Parsing is now being included correctly

Added
- Lark based verilog parsing to vastly speed up reading verilog netlists

Changed
- Replaced memory elements with a more general blackbox-based scheme

Fixed
- Image link in README is external so that it will appear in pypi