Cocotbext-pcie

Notable changes in this release:

Simulation models:

- Fix some bugs related to devices with multiple functions
- Improve max latency timer computation based on PCIe spec
- Fix typo in `Tlp.unpack_header()`
- Fix link control register bits
- Fix ERR_FATAL message type
- Add PTM message types
- Support splitting read requests on every RCB
- Implement CRS software visibility
- For downstream ports, only enumerate device 0
- Handle CRS during enumeration

IP core models:

- Fix logging when using `from_entity()` in P-Tile, S10, and US/US+ models
- Add P-Tile port number
- Enforce RX completion buffer occupancy in P-Tile, S10, and US/US+ models
- Fix cfg_rcb_status in US/US+ models
- Add local error reporting in US/US+ models
- Update S10, P-Tile, and US/US+ models based on RX completion buffer tests

Notable changes in this release:

Simulation models:

- Support issuing non-posted operations in parallel

IP core models:

- Fix RcSink discontinue bit offset in US/US+ models
- Improve tag handling in US/US+ models
- Improve tag handling in Intel models
- Refactor bus master enable and discontinue checks in US/US+ models
- Add support for internal core tag management in US/US+ models
- Pause US/US+ sources and sinks when idle

Notable changes in this release:

- Widen flow control counters and mask off appropriately so P-Tile model can report the correct values

Notable changes in this release:

IP core models:

* Add PCIe HIP model for Intel Stratix 10 DX/Agilex P-Tile

Notable changes in this release:

IP core models:

* Fix framing for 256 bit RC interface when TLP straddling is enabled in UltraScale model

Notable changes in this release:

IP core models:

* Fix handling of byte enable and sequence number in RQ tuser sideband when TLP straddling is enabled in UltraScale+ model