Corsair

* Fix rolh/roll missing latch bug
* Fix constants comparison on address in vhdl
* Fix C/C++ header generation

* Various bug fixes

* Fix overlapping of bitfiled names in rendered images for registers

* Fix an issue where the input globconfig file was not being applied to generators

**Reworking the entire project almost from scratch. Lots of breaking changes.**

* New configuration file format (INI)
* New file generation flow (more clear)
* Do refactoring of all core modules
* Add enums
* Add C header generator
* Add Verilog header generator
* Add SystemVerilog package generator
* Embed bus interface (AXI-Lite, APB, Avalon-MM) into a register map
* Add VHDL register map generator
* Add plenty of examples
* Rework of documentation
* Update the tests
* Many minor tweaks and fixes

* Fix Markdown table row endings.
* Add 'Reserved' bitfields to Markdown.
* Fix installation guides.
* Implement access_strobes attribute for register.
* Implement complementary registers.
* Implement write_lock attribute for register.
* Implement FIFO bitfield modifier.
* Implement AXI-Lite to Local Bus bridge on Verilog.
* Implement Avalon-MM to Local Bus bridge on Verilog.