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* Updated parser init/free routines to make parser params work.
* Modularized heuristics.
* Added constrained function.
* Added problem num_extra_vars bug fix for constrained functions.
* Added "apply" method to heuristic.
* Made heuristic accept array of constraint pointers instead of linked list of constraints.
* Added contingency name and corresponding setter/getter.
* Updated json float sig digits from 11 to 16.
* Modular flow routines for branches.
* Added array attribute getters for network component structs.
* Moved constraint alloc/clear to "parent" struct (advanced custom constraints can extend).
* Made constraint init/free optional.
* Removed NBOUND constraint.
* Changed PVPQ switching heuristic to HEUR_PVPQ_SWITCHING for consistency with constraint.
* Renamed LBOUND constraint to BOUND.
* Moved function alloc/clear to "parent" struct (advanced custom functions can extend).
* Made function init/free optional.
* Changed count/analyze/eval/etc loop to be bus-based.
* Fixed bug with PVPQ switching constraint when no Q vars.
* Voltage dependent loads: comp_cp, comp_cq, comp_ci, comp_cj, comp_cg, and comp_cb attributes, is_vdep routine, LOAD_PROP_VDEP property, updated parsers.
* Added CONSTR_LOAD_VDEP constraint.
* DC buses, DC branches, and VSC converters for HVDC.
* Added shunt types and net counters.
* Added bus property BUS_PROP_VSET_REG and "is_v_set_regulated" method.
* CSC converters for HVDC.
* FACTS devices.
* Extended count/analyze/eval framework (and added safeguards to existing constr/func/heur) to loop through ac and then dc buses.
* Added regulating object interface.
* Added constraint for VSC DC voltage control (CONSTR_VSC_DC_VSET).
* Added constraint for VSC DC power control (CONSTR_VSC_DC_PSET).
* Added constraint for HVDC power balance (CONSTR_HVDCPF).
* Added constraint for VSC equations (CONSTR_VSC_EQ).
* Updated PVPQ switching constraints to use reg object interface.
* Updated PVPQ switching heuristic to use reg object interface.
* Added function for encouraging VSC DC power control (FUNC_VSC_DC_PSET).
* Changed CONSTR_REG_GEN to CONSTR_REG_VSET and made it use the reg object interface and changed name to "voltage set point regulation".
* Changed bus sens_v_reg_by_gen to sens_v_set_reg.
* Made PVPQ switching heuristic consider reg buses that are slack (to be consistent with constr_REG_VSET).
* Added switching constraint for power factor regulation (CONSTR_REG_PF_SWITCH).
* Added switching heuristic for power factor regulation (HEUR_REG_PF_SWITCH).
* Added smooth constraint for power factor regulation (CONSTR_REG_PF).
* Added switching constraints for FACTS active/reactive power control (CONSTR_FACTS_PSET_SWITCH and CONSTR_FACTS_QSET_SWITCH).
* Added functions for FACTS active/reactive power control (FUNC_FACTS_PSET and FUNC_FACTS_QSET).
* Added constraint for FACTS equations (CONSTR_FACTS_EQ).
* Added load "in_service" field, getter and setter. Not used anywhere.
* Added routines for updating PQ components of load according to provided weights.
* Added very basic CSC constraints and functions (CONSTR_CSC_EQ, CONSTR_CSC_DC_PSET, CONSTR_CSC_DC_VSET, FUNC_CSC_DC_PSET).
* Added JSON support (read/write) for new components (vdep loads, csc, vsc, facts, dc bus, dc branch).
* Added switched shunt control mode (discrete, continuous) and rounding capability.
* Added network routing for rounding susceptance of discrete switched shunts and count.
* Added branch routine for using power flow count/analyze/eval subroutines to construct Jacobian of (P_km, Q_km) or (P_mk, Q_mk).
* Removed graphviz interface and dependency.
* Removed number of actions from network properties.
* Added redundant buses.
* Added output_level to nework component summary output.