Python2verilog

What's Changed
* Restructured codegen by WorldofKerry in https://github.com/WorldofKerry/Python2Verilog/pull/181
* Update README.md by WorldofKerry in https://github.com/WorldofKerry/Python2Verilog/pull/180
* Reduced hardware usage with nested for loops by WorldofKerry in https://github.com/WorldofKerry/Python2Verilog/pull/182


**Full Changelog**: https://github.com/WorldofKerry/Python2Verilog/compare/v0.4.1...v0.4.2

What's Changed
* Changed prefix of protocol signals by WorldofKerry in https://github.com/WorldofKerry/Python2Verilog/pull/178


**Full Changelog**: https://github.com/WorldofKerry/Python2Verilog/compare/v0.4.0...v0.4.1

What's Changed
* Added for loop support without explicit instance variable by WorldofKerry in https://github.com/WorldofKerry/Python2Verilog/pull/177


**Full Changelog**: https://github.com/WorldofKerry/Python2Verilog/compare/v0.3.0...v0.4.0

What's Changed
* Added support for regular functions by WorldofKerry in https://github.com/WorldofKerry/Python2Verilog/pull/172


**Full Changelog**: https://github.com/WorldofKerry/Python2Verilog/compare/v0.2.10...v0.3.0

What's Changed
* Added limit to number of yields in testbench by WorldofKerry in https://github.com/WorldofKerry/Python2Verilog/pull/166
* Fixed done correctness bug by WorldofKerry in https://github.com/WorldofKerry/Python2Verilog/pull/167
* Enhanced exclusive variables with exclusion group by WorldofKerry in https://github.com/WorldofKerry/Python2Verilog/pull/168


**Full Changelog**: https://github.com/WorldofKerry/Python2Verilog/compare/v0.2.9...v0.2.10

What's Changed
* Improved error handling by WorldofKerry in https://github.com/WorldofKerry/Python2Verilog/pull/165


**Full Changelog**: https://github.com/WorldofKerry/Python2Verilog/compare/v0.2.8...v0.2.9