Rapidwright

**Release Notes:**
- [DesignTools] Fix routethru corner case in fullyUnplaceCellHelper() (1157)
- Add option to uniquify copied cells (1156)
- [DesignTools] Ensure cell pin has a logical connection before attempting to unroute it (1154)
- [DesignTools] Unroutes both CLK pins on a BRAM when requested (1151)
- [EDIF] Fix Export of Single Bit Busses (1147)
- Fixes to enable BlockStitcher to run (1134)
- Enables batching of SitePinInst removals during MakeBlackBox (1142)
- Routing Heat Map Example (1145)
- When adding Modules to Designs, make EDIF cell names unique if name collides

API Additions:
- com.xilinx.rapidwright.design.Design "public boolean removeSiteInst(SiteInst instance, boolean keepSitePinRouting,
- com.xilinx.rapidwright.design.Design "public Map<SiteTypeEnum, Set<String>> getCompatiblePlacements(Unisim u)"
- com.xilinx.rapidwright.design.Design "public static Map<SiteTypeEnum, Set<String>> getCompatiblePlacements(FamilyType family, Unisim u)"

**Release Notes:**
- Adds an Override Flag for Advanced Flow Settings in Designs (1135)
- Test for SiteInst.isEmpty() (1128)
- Tests for Versal BEL flags and site unrouting (1125)
- [LUTTools] Versal pin swapping fixes (1130)
- [DesignTools] foreachConnectedBELPin() to walk through Versal IMRs (1129)
- [DesignTools] updatePinsIsRouted() to return num unrouted sinks (1131)
- [TestDesign] Add testPlaceCellPinMappings() (1122)
- [RWRoute] Small cleanup; enable CUFR by default (1126)
- RWRoute preprocessing fixes (1119)
- Enables setting Advanced Flow Flags for Designs
- Corrects and Adds BEL flags; fixes unroute site net for Versal
- [Cell] Fixes to P2L and L2P

API Additions:
- com.xilinx.rapidwright.design.Cell "public void fixCell(boolean isFixed)"
- com.xilinx.rapidwright.design.Cell "public boolean isCellFixed()"
- com.xilinx.rapidwright.design.Design "public boolean isAdvancedFlow()"
- com.xilinx.rapidwright.design.Design "public void setAdvancedFlow(boolean val)"
- com.xilinx.rapidwright.design.SiteInst "public boolean isEmpty()"
- com.xilinx.rapidwright.device.BEL "public boolean isCEIMR()"
- com.xilinx.rapidwright.device.BEL "public boolean isSliceIMRClkMod()"

**Release Notes:**
- The memory usage improvements in this release reduce a routed DCP footprint by 10-20%
- Remove reliance on gap routing test (1117)
- [ModuleInst] Fix placement behavior when requesting no overlaps (1108)
- [RWRoute] Clock router for Versal architecture (1102)
- Various preprocessing fixes for Versal routing (1115)
- [CUFR] CUFR and PartialCUFR to default to --hus (1111)
- [TestNet] Improve testSetPinsMultiSrcStatic to track many sources (1082)
- Changes to support new array-based cell pin mappings (1101)
- Update tests to reflect bug fixes and minor behavior changes (1110)
- [RWRoute] Yet more cleanup (1107)
- [RWRoute] Preserve nodes of Laguna sinks (1104)
- [GlobalSignalRouting] routeStaticNets() to take a list of static pins (1105)
- [RWRoute] Fix typo -- not an exclusive sink (1106)
- [RWRoute] Versal optimizations (1093)
- [RWRoute] RouteNode.setType() to accept any locals (1103)
- [RWRoute] Further divide LOCAL nodes into EAST/WEST for UltraScale(+) (1098)
- [Utils] isClocking() to include TileTypeEnum.CMT_L (1100)
- TileGroup and DeviceBrowser Improvements (1094)
- [RWRoute] Divide nodes into LOCAL and NON_LOCAL (1095)
- Update actions and do not limit to 5G RAM (1092)
- [HandPlacer] Cleanup snapping code in hand placer (1091)
- [LUTTools] Add zero padding to LUT INIT strings (1090)
- [NetTools] Add getNodeTrees() method and NodeTree class (1089)
- [YosysTools] Add synthXilinx() wrapper for Yosys (1086)
- [EDIFWriteLegalNameCache] busCollisionRenames to be a ConcurrentHashMap (1088)
- Add ReportRouteStatus utility (1087)
- [RWRoute] Signal router for Versal architecture (1077)
- [FileTools] Add runCommand(String[] ...) & getExecutablePath(String) (1085)
- [RouterHelper] findPathBetweenNodes() allow clocking if src/sink is so (1083)
- [RouterHelper] projectOutputPinToINTNode() to breadth-first-search (1081)
- [RouterHelper] projectInputPinToINTNode() to return solitary node (1080)
- [RouterHelper] findPathBetweenNodes() to ignore clocking tiles (1079)
- [RouterHelper] invertPossibleGndPinsToVccPins() to support Versal LUTs (1078)
- [DesignTools] Fix createCeSrRstPinsToVCC() for US BRAMs (1075)
- [DesignTools] Add LDCE/LDPE to types that need VCC (1076)
- [NetTools] Add NetTools.isGlobalClock() (1057)
- Static router for Versal architecture (1073)
- [EDIFNetlist] getPhysicalPins() to call getPhysical{Gnd,Vcc}Pins() (1074)
- Fix Null SLR References in Tiles in xcvp1902
- Add Implements Serializable to All RapidWright Classes
- [SiteInst] Improve memory usage of site routing using array instead of maps
- [Cell] Changes pin mappings from a map to an array to improve memory usage
- [BEL] Deprecate isSRIMR() in favour of more general isIMR()
- [Tile] Add getMaxUniqueAddress()
- [Net] Add support for multiple output sources

API Additions:
- com.xilinx.rapidwright.design.Cell "public Pair<BELPin, String> getFirstPhysicalPinMapping()"
- com.xilinx.rapidwright.design.Cell "public int getUsedPhysicalPinsCount()"
- com.xilinx.rapidwright.design.Cell "public Set<String> getUsedPhysicalPins()"
- com.xilinx.rapidwright.design.Cell "public String[] getPhysicalPinMappings()"
- com.xilinx.rapidwright.design.Cell "public boolean usesPhysicalPin(String physicalPinName)"
- com.xilinx.rapidwright.design.Design "public boolean placeCell(Cell c, Site site, BEL bel, String[] physPinMappings)"
- com.xilinx.rapidwright.design.Net "public List<SitePinInst> getAlternateSources()"
- com.xilinx.rapidwright.device.BEL "public boolean isIMR()"
- com.xilinx.rapidwright.device.Tile "public int getMaxUniqueAddress()"

**Release Notes:**
- [RWRoute] Further cleanup (1070)
- [PhysNetlistReader] Call SiteInst.setDesign() even for STATIC_SOURCEs (1071)
- [GlobalSignalRouting] Fix VCC routing for UltraScale (1068)
- [RWRoute] Cleanup static router and RouterHelper (1059)
- [PartialRouter] Disable ripup in global/static routing (1067)
- [TestDesign] Add test for net ordering of >= 2022.1 DCPs (1054)
- [TestBEL] Add testDIFFsAreNotFF() (1062)
- Test for Design.retargetPart() (1061)
- [EDIF] Fixes rare bus renaming collision (1065)
- [RWRoute] Always clear prev pointer of unpreserved RouteNode-s (1056)
- [LaunchTestsOnLsf] Invoke java with assertions enabled (1066)
- [LaunchTestsOnLsf] Invoke java with assertions enabled (1063)
- Fix testRouteStaticNet() to avoid site pins, and fix golden values (1064)
- [GitHub Actions] Migrate to upload-artifactv4 (1058)
- Add recursive partitioning ternary tree (RPTT) (1055)
- Add support for vu19p tiles in bitstream
- [Design] createModuleInst() to not create duplicate STATIC_SOURCE-s
- Removes all instances of enum.hashCode()
- [Node] equals() to use instanceof for subclass-awareness
- Retarget & relocate an existing design to a new part and location
- Fixes issue related to non-deterministic Net order upon multi-threaded DCP load
- Fix BEL.isFF() based on BELTypes
- Fix missing Design.getSeries()

API Additions:
- com.xilinx.rapidwright.design.Design "public boolean retargetPart(Part targetPart, int tileXOffset, int tileYOffset)"

**Release Notes:**
- Creating a standalone entry point to relocate DCPs (1047)
- [Interchange] Reorders tile types and tiles to follow their Vivado index (1039)
- [DesignTools] Conform to Vivado *RST* pin inversion site routing configuration (1053)
- Fix for design merging, including designs with encrypted cells (1035)
- Filters out comments in XDC while parsing clk constraints (1037)
- Assign an empty list when path finding for direct connections fails (1052)
- Make LogicalNetlistToEdif not expand macros by default (1051)
- [Interchange] Fixes to support Versal designs via Interchange (1040)
- EDIF cleanup preventing singleton cells/libraries from attaching to user designs (1050)
- [RWRoute] Refactoring/cleanup/preparation for multi-threading (1046)
- Add Hybrid Updating Strategy (HUS) (1043)
- [TestSiteInst] Add test for unrouting through FF routethru cells (1041)
- [TestPIP] Test PIP constructor for reversed wires (1045)
- [RWRoute] Preserve primary source nodes on connections (1038)
- Small Interchange/PhysNetlistReader/VivadoTools improvements (1042)
- [UnisimManager] Use EDIFLibraryBuiltin for primitive/macro libs
- Avoids NPE when site routing BRAMs
- Fix isCarry() for Versal devices
- Resolves PIP constructor issue for reversed PIPs
- [SiteInst] unrouteIntraSiteNet() to handle FF routethru cells

API Additions:
- com.xilinx.rapidwright.design.Design "public Series getSeries()"
- com.xilinx.rapidwright.design.SiteInst "public SitePIP getUsedSitePIP(BEL bel)"

**Release Notes:**
- [VivadoTools] Source *_load.tcl from same dir as DCP (1032)
- Test that PIP.isReversed() is correct (1024)
- Add TestSite.testGetIntTile() (1022)
- [EDIFTools] writeTclLoadScriptForPartialEncryptedDesigns abspath (1029)
- Adding HDIOB types (1028)
- Test for site routing from raw placed design (1000)
- [RWRoute] Do not NPE on encrypted netlists (1025)
- [RWRoute] Do not assume Y = 0 has Laguna tiles, since it could be HBM device (1026)
- Adds UNKWN state for LSFJobs (1027)
- Adding legacy support for u280 (1021)
- Remove flawed loop intended to for encrypted cell removal (1023)
- [DesignTools.makeBlackBox()] Fixes an issue of removing CARRY blocks fed by routethrus (1009)
- Fix null netlist pointer on expanded macro children (1008)
- [Interchange] Device Resources Verifier Fixes (1014)
- Fix ConcurrentModificationError (1015)
- [EDIFTools] Adding method to create a flat netlist from a hierarchical one (1006)
- Adding HBM ComponentTypes (1007)
- Test for wire/node mismatch reported in 983 (1005)
- 3.6% memory reduction usage for large placed designs (de-duplication of cell pin strings)
- Add missing pin entry for BUFG_GT when tracking INT tile connections
- Fixes rare DCP write issue with stubbed bi-directional PIPs (more common on DFX designs)
- Fix for reversed flag on PIPs
- Addresses issue with Net.getBufferDelay() by checking for null wire names
- Fixes two site routing issues