Rapidwright

**Release Notes:**
- [RWRoute] Further cleanup (1070)
- [PhysNetlistReader] Call SiteInst.setDesign() even for STATIC_SOURCEs (1071)
- [GlobalSignalRouting] Fix VCC routing for UltraScale (1068)
- [RWRoute] Cleanup static router and RouterHelper (1059)
- [PartialRouter] Disable ripup in global/static routing (1067)
- [TestDesign] Add test for net ordering of >= 2022.1 DCPs (1054)
- [TestBEL] Add testDIFFsAreNotFF() (1062)
- Test for Design.retargetPart() (1061)
- [EDIF] Fixes rare bus renaming collision (1065)
- [RWRoute] Always clear prev pointer of unpreserved RouteNode-s (1056)
- [LaunchTestsOnLsf] Invoke java with assertions enabled (1066)
- [LaunchTestsOnLsf] Invoke java with assertions enabled (1063)
- Fix testRouteStaticNet() to avoid site pins, and fix golden values (1064)
- [GitHub Actions] Migrate to upload-artifactv4 (1058)
- Add recursive partitioning ternary tree (RPTT) (1055)
- Add support for vu19p tiles in bitstream
- [Design] createModuleInst() to not create duplicate STATIC_SOURCE-s
- Removes all instances of enum.hashCode()
- [Node] equals() to use instanceof for subclass-awareness
- Retarget & relocate an existing design to a new part and location
- Fixes issue related to non-deterministic Net order upon multi-threaded DCP load
- Fix BEL.isFF() based on BELTypes
- Fix missing Design.getSeries()

API Additions:
- com.xilinx.rapidwright.design.Design "public boolean retargetPart(Part targetPart, int tileXOffset, int tileYOffset)"

**Release Notes:**
- Creating a standalone entry point to relocate DCPs (1047)
- [Interchange] Reorders tile types and tiles to follow their Vivado index (1039)
- [DesignTools] Conform to Vivado *RST* pin inversion site routing configuration (1053)
- Fix for design merging, including designs with encrypted cells (1035)
- Filters out comments in XDC while parsing clk constraints (1037)
- Assign an empty list when path finding for direct connections fails (1052)
- Make LogicalNetlistToEdif not expand macros by default (1051)
- [Interchange] Fixes to support Versal designs via Interchange (1040)
- EDIF cleanup preventing singleton cells/libraries from attaching to user designs (1050)
- [RWRoute] Refactoring/cleanup/preparation for multi-threading (1046)
- Add Hybrid Updating Strategy (HUS) (1043)
- [TestSiteInst] Add test for unrouting through FF routethru cells (1041)
- [TestPIP] Test PIP constructor for reversed wires (1045)
- [RWRoute] Preserve primary source nodes on connections (1038)
- Small Interchange/PhysNetlistReader/VivadoTools improvements (1042)
- [UnisimManager] Use EDIFLibraryBuiltin for primitive/macro libs
- Avoids NPE when site routing BRAMs
- Fix isCarry() for Versal devices
- Resolves PIP constructor issue for reversed PIPs
- [SiteInst] unrouteIntraSiteNet() to handle FF routethru cells

API Additions:
- com.xilinx.rapidwright.design.Design "public Series getSeries()"
- com.xilinx.rapidwright.design.SiteInst "public SitePIP getUsedSitePIP(BEL bel)"

**Release Notes:**
- [VivadoTools] Source *_load.tcl from same dir as DCP (1032)
- Test that PIP.isReversed() is correct (1024)
- Add TestSite.testGetIntTile() (1022)
- [EDIFTools] writeTclLoadScriptForPartialEncryptedDesigns abspath (1029)
- Adding HDIOB types (1028)
- Test for site routing from raw placed design (1000)
- [RWRoute] Do not NPE on encrypted netlists (1025)
- [RWRoute] Do not assume Y = 0 has Laguna tiles, since it could be HBM device (1026)
- Adds UNKWN state for LSFJobs (1027)
- Adding legacy support for u280 (1021)
- Remove flawed loop intended to for encrypted cell removal (1023)
- [DesignTools.makeBlackBox()] Fixes an issue of removing CARRY blocks fed by routethrus (1009)
- Fix null netlist pointer on expanded macro children (1008)
- [Interchange] Device Resources Verifier Fixes (1014)
- Fix ConcurrentModificationError (1015)
- [EDIFTools] Adding method to create a flat netlist from a hierarchical one (1006)
- Adding HBM ComponentTypes (1007)
- Test for wire/node mismatch reported in 983 (1005)
- 3.6% memory reduction usage for large placed designs (de-duplication of cell pin strings)
- Add missing pin entry for BUFG_GT when tracking INT tile connections
- Fixes rare DCP write issue with stubbed bi-directional PIPs (more common on DFX designs)
- Fix for reversed flag on PIPs
- Addresses issue with Net.getBufferDelay() by checking for null wire names
- Fixes two site routing issues

**Release Notes:**
Notes:
- Support for Vivado 2024.1 DCPs and devices
- Support to write DCPs with physDB components with Params.RW_WRITE_DCP_2024_1
- 2024.1 DCP Write Test (997)
- Updates to support 2024.1 DCP writing (995)
- Add FileTools.getAutoBufferedInputStream() with zstd auto-detect (990)
- BlockPlacer2: Fix off by one error in selecting module instance to move (987)
- Fix PolynomialGenerator and TestDCPSave tests (982)
- Use exit code 1 if any LSF job failed (981)
- Fixes issues around Node->Wire equivalence (407)

API Additions:
- com.xilinx.rapidwright.device.Device "public boolean hasModularSLRs()"
- com.xilinx.rapidwright.device.Wire "public boolean isConnected()"
- com.xilinx.rapidwright.device.Wire "public boolean isTiedToVCC()"
- com.xilinx.rapidwright.device.Wire "public boolean isTiedToGND()"
- com.xilinx.rapidwright.device.Wire "public boolean isTied()"

API Removals:
- com.xilinx.rapidwright.device.Node "public int getWire()"
- com.xilinx.rapidwright.util.RapidWright "*"

**Release Notes:**
Notes:
- Use new Cell.{LOCKED,PORT_TYPE,isPortCell()} (977)
- Remove some pre-2023.2.2 workarounds (978)
- [RWRoute] Fix logical driver flag setting for DCP write (979)
- Add explicit use case for a Jython script in --help (980)
- [VivadoTools] Add placeDesign() and getWorstSetupSlack() (975)
- [RWRoute] Consider all nets in timing-driven routing (976)
- [DCP] Test Design.writeCheckpoint() when using existing EDIF (965)
- Work around for multi-inverter BEL in DSP58 (969)
- [DesignTools.makeBlackBox()] Fix for 967 (970)
- [RWRoute,PhysNetlistReader] Set logical driver on PIPs (973)
- [SLRCrosserGenerator] Adds North/South parameterizable bus widths; some error checking (972)
- [EDIFTokenizer] Account for byte size of UTF-8 characters correctly (962)
- [VivadoTools] writeBitstream to not delete DCP parent dir (+more) (955)
- [RWRoute] Preserve [A-H]_O node when [A-H]MUX used as static src (954)
- [GlobalSignalRouter] No intra site routing for new static source pins (953)
- [EDIFPropertyValue] Fix getBooleanValue() NPE (952)
- [PhysNetlistReader] Fix checkConstantRoutingAndNetNaming() (951)
- [RWRoute] When removing unused source SPI restore intra-site routing (949)
- [RWRoute] Tidy up createNetWrapperAndConnections() (950)
- Fix EDIFPropertyValue.getBooleanValue() (948)
- [RWRoute] Replace main src with altsrc if main is unused (945)
- [RWRoute] Fix comment Eastern -> Western (943)
- RouterHelper.invertPossibleGndPinsToVccPins() to invert static LUT inputs (910)
- [TestRWRoute] Stop skipping some tests when < 8GB (941)
- Temporary workaround to clear logical net after Net.rename() (942)
- Known failing test for EDIFHierPortInst.getRoutedSitePinInst() (577)
- Known failing test for Tile.getSites() result different to Vivado (745)
- Known failing test for BITSLICE_CONTROL output pin projection (559)
- Add known failing testcase for 756 (758)
- Update RWRouteConfig.java (940)
- [RWRoute] Add --lutRoutethru option (932)
- [RWRoute] Do not pin swap SRL (shift register) cells (939)
- [LUTTools] LUT pin swapping fixes (938)
- Net.rename() to clear logical hier net
- Fix regarding issue around bitstream header
- Fixes issue when site wire lacks GND tag

API Additions:
- com.xilinx.rapidwright.bitstream.Bitstream "public boolean writeBitstream(Path path)"
- com.xilinx.rapidwright.bitstream.Frame "public List<BitLocation> getDiff(Frame otherFrame)"
- com.xilinx.rapidwright.design.Cell "public static final String LOCKED = "<LOCKED>";
- com.xilinx.rapidwright.design.Cell "public static final String PORT_TYPE = "<PORT>";
- com.xilinx.rapidwright.design.Cell "public boolean isPortCell()"
- com.xilinx.rapidwright.design.Cell "public String getPropertyValueString(String key)"
- com.xilinx.rapidwright.design.Design "public void writeCheckpoint(String dcpFileName, String edfFileName, CodePerfTracker t)"
- com.xilinx.rapidwright.design.Design "public void writeCheckpoint(Path dcpFileName, Path edfFileName, CodePerfTracker t)"
- com.xilinx.rapidwright.design.Design "public void detachNetlist(Predicate<Cell> preserveCellProperties)"
- com.xilinx.rapidwright.device.BEL "public static BEL getBEL(Device device, SiteTypeEnum siteTypeEnum, String belName)"
- com.xilinx.rapidwright.device.PIP "public boolean isArcInverted()"
- com.xilinx.rapidwright.device.PIP "public void setIsLogicalDriver(boolean isLogicalDriver)"
- com.xilinx.rapidwright.device.SitePIP "public int getIndex()"
- com.xilinx.rapidwright.device.SitePIP "public static SitePIP getSitePIP(Device device, SiteTypeEnum siteTypeEnum, int sitePIPIndex)"

**Release Notes:**
- Add EDIFHierCellInst.isUniquified() (918)
- [RWRoute] RouteNode to extend Node (916)
- [DesignComparator] Fix whitespace (937)
- RouteThruHelper.isRouteThruPIPAvailable(Design, WireInterface, WireIn (915)
- Create a common interface for Node and Wire Objects (892)
- DesignComparator - compares place and route data (931)
- DesignTools.createMissingSitePinInsts() to infer SitePinInsts more smartly (936)
- LUTTools.swapLutPinsFromPIPs() to warn when site pin not found (934)
- [PhysNetlistReader] Warn and omit if PIP not found (933)
- [PhysNetlistWriter] Handle PORT cells in GTY tiles (930)
- [PhysNetlistWriter] Assume static net output BELPins to be sources too (929)
- [PhysNetlistWriter] Fix stubs on static nets (928)
- Get a Boolean from EDIFPropertyValue (926)
- [PhysNetlistWriter] Infer direction of IOB's PAD.PAD BEL pin (927)
- [RouteThruHelper] Move assertions, improve tests (925)
- [RWRoute] Don't swap dist RAMs on 'H' BELs since A and WA are shared (924)
- [PhysNetlistWriter] Recognize static source BELPins (e.g. LUT outputs) (923)
- [RWRoute] Analyze a tile below the topmost arbitrary one (921)
- Adding test for IOB placement (903)
- [DesignTools.makeBlackBox()] Fixes routing issues in makeBlackBox() (919)
- [ECOTools] Inline cell insertion (917)
- RouterHelper.invertPossibleGndPinsToVccPins() to work on all invertible pins (911)
- [RWRoute] GlobalSignalRouting static net router to use [A-H]MUX outputs (914)
- [RWRoute] Fix exception for unrouteable connections (913)
- Declare gradle dependency explicitly (909)
- Fixes [Versal BELAttr] Parsing issue 912
- Add site pins when site routing through inverter BELs
- Fix UltraScale+ IBUF site routing
- Fix DSP pin mapping removals during site routing
- Adds support for special clock Node flag present in Versal designs

API Additions:
- com.xilinx.rapidwright.device.Node "public Node(Node node)"
- com.xilinx.rapidwright.device.Package "public synchronized PackagePin getPackagePin(Site site)"
- com.xilinx.rapidwright.device.Package "public String getPackagePinName(Site site)"