Riscemu

- BugFix: Fix `malloc` implementation from being just wrong to being right (I think?)
- BugFix: Fix `MMU.translate_address` to actually return the best match (wow!)
- Feature: The instruction trace now contains register and symbol values starting at verbosity level 3
- BugFix: RVDebug got better at finding out if a float or int register was meant

- Feature: Canonicalize register names when parsing, converting e.g. `x0 -> zero` or `fp -> s0`.
- Feature: Added support for `fcvt.d.w[u]` and `fcvt.w[u].d` instructions
- BugFix: Fixed that registers were treated as UInt32s instead of Int32 (this may have caused subtle bugs before)
- Feature: Added the remainder of the `M` extension
- BugFix: Fixed a bug in the overflow behavior of `mulh`
- BugFix: Fix faulty length assertion in `jalr`

- BugFix: Fix missed import in core.simple_instruction

- BugFix: Found and added some missing floating point registers (`ft8` to `ft11`)
- Feature: Add frep support to the snitch emulation
- Feature: Add support for 64-bit floats to the snitch Xssr emulation

- Feature: Adding support for 64 bit floating point operations
- BugFix: Fix a bug where `-o libc` would fail with packaged versions of riscemu
- BugFix: Fix `__all__` to now properly work (use name strings instead of values)

- Dev: Add `__all__` to `riscemu.{core,instructions,decoder}` modules to make pyright in other projects happy
- Perf: very minor fix related to not converting values twice when loaded from memory