Siliconcompiler

=========================================

**Minor:**

* Added helper functions to tcl to make accessing schema information easier.
* Added helper functions to allow tools to have consistent behavior around picking from pdk/library/option variables during setup.
* Ensure the remote client downloads the final results from the remote to get any logs and error messages.

* Tools:

* openroad: fixed default routing via settings.
* klayout: made hide_layer variable more consistent with klayouts layer information, and added support for .gz file handling in show and screenshotting tasks.

=========================================

**Minor:**

* Switch to use templates for generating tool files instead of python print statements to make it easier to maintain.
* Added logic depth to schema metrics.

* Tools:

* yosys: added support for handling hierarchy selection with globbing, added better handling of library merging to ensure liberty templates are properly copied in.
* openroad: added support for extracting logic depth of the design and added irdrop extraction to tool driver.

=========================================

**Minor:**

* General cleanup of documentation building.

* Tools:

* yosys: added support for specifying blackbox models via ['tool', 'yosys', 'task', 'syn_asic', 'var', 'blackbox_modules']

=========================================

**Minor:**

* Fixed packaging extraction when downloading from github.
* Fixed remote run file retrieval to avoid errors when extracting and moving files.

* Tools:

* vpr: added support for show and screenshoting tasks.

=========================================

**Minor:**

* Update remote code to honor constraints transmitted by the remote runner.
* Add fall back to package locking when file system locking is not available.
* Fixed handling of github artifact packages.
* Added build scripts for ubuntu22.

* Tools:

* vpr: add reporting images to tool driver, these can be disabled via ['tool', 'vpr', 'task', 'place' or 'route', 'var', 'enable_images'] = 'false'.

=========================================

**Minor:**

* Fixed handling of files with codec errors.
* Update package lock file handling to avoid race conditions in parallel flows.

* Tools:

* yosys: minor code cleanup in FPGA flow.
* vpr: add support for clock routing.
* surelog: added wrapper comments in output file for parsing to indicate where segments of code came from.