What's Changed
* dvine TSP with precedence constraints, sim sobol seq TY-Cheng in https://github.com/TY-Cheng/torchvinecopulib/commit/c451e67254c8b145700871e3c4eca01eefa3ab65
* sampling order (tpl_sim) and vcp_from_sim by TY-Cheng in https://github.com/TY-Cheng/torchvinecopulib/pull/25
* Update python-package.yml by TY-Cheng in https://github.com/TY-Cheng/torchvinecopulib/pull/28
**Full Changelog**: https://github.com/TY-Cheng/torchvinecopulib/compare/v2024.7.1...v2024.10.0