Uart

- adds possibility to modify pulse length - 34

- always ask before overwriting except when instructed otherwise
- fixed an issue that caused non-default compilation library not be saved to json
- added command-line options regarding output directory and overwriting of files
- added PDF generation of docs - requires pdflatex in PATH and texlive installed
- allow for updating of top-level VHDL file without overwriting user logic - 7

- fixed bug that caused an error when creating a sl field - 28
- updated docs and added requirements.txt for easy package execution of development version
- added check for base address in VHDL logic
- implemented base address as generic (removed from package) - 27
- implemented optional base address offset feature - multiple instances can now be separated by fixed offset
- optional bus package compilation library - defaults to work
- added internal axi_out signal in module top level - makes it possible to read values from this - to do certain specific operations that are not supported by the tool
- removed unused AXI4-lite signals - wstrb, awprot and arprot - 30
- added mask to fields in header files - 29