Yasimavr

What's Changed
core improvements :
* Debug framework changes by clesav in https://github.com/clesav/yasimavr/pull/84
* EEPROM parameter independent from flash page size by clesav in https://github.com/clesav/yasimavr/pull/85
* Adding AVR reset controller model by clesav in https://github.com/clesav/yasimavr/pull/86
* Misc API changes by clesav in https://github.com/clesav/yasimavr/pull/88
* AVR WDT model by clesav in https://github.com/clesav/yasimavr/pull/91
* Device config changes by clesav in https://github.com/clesav/yasimavr/pull/92
* GDB stub additions by clesav in https://github.com/clesav/yasimavr/pull/94
* Corrected simrun race condition and real-time mode by clesav in https://github.com/clesav/yasimavr/pull/96
* simdump additions by clesav in https://github.com/clesav/yasimavr/pull/97
* ACP config & model corrections by clesav in https://github.com/clesav/yasimavr/pull/99
* Misc bugs correction by clesav in https://github.com/clesav/yasimavr/pull/101

Device library:
* Added config alias system by clesav in https://github.com/clesav/yasimavr/pull/93
* Added Attiny 0series to device library by clesav in https://github.com/clesav/yasimavr/pull/98

Others:
* Examples correction by clesav in https://github.com/clesav/yasimavr/pull/100
* Added python 3.13 windows build by clesav in https://github.com/clesav/yasimavr/pull/90
* Cleaned sdist and added version constant to core lib by clesav in https://github.com/clesav/yasimavr/pull/83
* package path correction by clesav in https://github.com/clesav/yasimavr/pull/95

**Full Changelog**: https://github.com/clesav/yasimavr/compare/v0.1.2...v0.1.3

What's Changed

Added support for bootloaders and self-programming features :
* Adding NVM section access control by clesav in https://github.com/clesav/yasimavr/pull/74
* Support for interrupt vector table advance features by clesav in https://github.com/clesav/yasimavr/pull/75
* XT architecture : Added support for BOOTLOCK & APCWP by clesav in https://github.com/clesav/yasimavr/pull/78
* AVR architecture : added support for lockbit by clesav in https://github.com/clesav/yasimavr/pull/79
* AVR architecture : added SPM peripheral model by clesav in https://github.com/clesav/yasimavr/pull/81

Others:
* CI action update by clesav in https://github.com/clesav/yasimavr/pull/76
* Simdump improvements by clesav in https://github.com/clesav/yasimavr/pull/77
* Build correction by clesav in https://github.com/clesav/yasimavr/pull/80

**Full Changelog**: https://github.com/clesav/yasimavr/compare/v0.1.1...v0.1.2

What's Changed
* Misc bug corrections by clesav in https://github.com/clesav/yasimavr/pull/61
* Fix GDB path by Erovia in https://github.com/clesav/yasimavr/pull/63
* Cycle timer API additions by clesav in https://github.com/clesav/yasimavr/pull/64
* FW symbols support by clesav in https://github.com/clesav/yasimavr/pull/65
* Remove unused attribute from Firmware class by clesav in https://github.com/clesav/yasimavr/pull/66
* Dev Descriptor changes by clesav in https://github.com/clesav/yasimavr/pull/67
* GDB_Stub bug correction by clesav in https://github.com/clesav/yasimavr/pull/68
* Device library bug corrections by clesav in https://github.com/clesav/yasimavr/pull/69
* New timer/counter (XT core) models by clesav in https://github.com/clesav/yasimavr/pull/70
* Updated sphinx dependencies by clesav in https://github.com/clesav/yasimavr/pull/71
* Added Device Library documentation by clesav in https://github.com/clesav/yasimavr/pull/72

New Contributors
* Erovia made their first contribution in https://github.com/clesav/yasimavr/pull/63

**Full Changelog**: https://github.com/clesav/yasimavr/compare/0.1...v0.1.1

What's Changed
* CLI: pretty print for model list
* Change FW areas to enum
* Sphinx doc generation
* Adding python 12 to Windows build
* Automatic testing using pytest
* Firmware & NVM rework
* Pin API rework
* GPIO Port model correction
* Readme correction

What's Changed
Build:
* Added delvewheel repair step to the build process on Windows, to deploy the DLL dependencies with the extension modules
C++ library :
* Comment rework to be Doxygen-readable and addition of Doxyfile
Bindings :
* Added comparison operators to reg_addr_t binding
Device configurations :
* Added TWI model and configuration for atmega48/88/168/328
* Added SPI model and configuration for atmega48/88/168/328

**Full Changelog**: https://github.com/clesav/yasimavr/compare/v0.0.3...v0.0.4