Cocotbext-spi

- BREAKING feature: replaced SpiSignals with SpiBus to follow cocotb-bus conventions
- feature: allow burst transmits from the master
- fix: error in master.write() documentation
- feature: added ADI ADXL345 device

Known Issues:
- different behavior for different simulators (icarus, incisive, and verilator)
- verilator behaves strangely with new SpiBus

- Fix bug with `__all__` import
- Test automatic release pipeline

Notable Changes in this Release:
- Fix bug resulting in incompatibility with Python 3.7
- Use pdm to facilitate packaging and distribution
- Add flake8 linter for code

Notable changes in this Release:
- Bug Fixes
- Add feature to ignore certain rx values in the master (not replicated in slave because implementation of slave is up to user)
- Switch to pyproject.toml and automatic versioning

Notable changes in this release:
- Changed the timing for SPI signals for both master and slave.
- Previously, ignored falling edges if a rising edge has not yet been seen. CPHA=0 indicates sample on rising edge, irrespective of idle clock polarity. This followed Analog Devices Timing Diagrams.
- Currently, CPHA=0 indicates sample on the first edge of sclk and write on the second. This is compliant with more vendors and matches the Wikipedia definition of the SPI modes.

Fixed SPI clocking for SPI modes 1,2,4.