Klayout

* Bugfix: %GITHUB%/issues/971 Double compare fails in LVS
* Bugfix: %GITHUB%/issues/972 CIF writer generates unreadable file with invalid cell or layer names
* Bugfix: %GITHUB%/issues/973 Enhanced timeout in package manager on large file download
* Bugfix: %GITHUB%/issues/979 Backup file generation fails with relative paths
* Bugfix: %GITHUB%/issues/982 Heal option for tiled XOR
* Bugfix: %GITHUB%/issues/983 Bug changing PCell parameters of multiple cell instance
* Bugfix: %GITHUB%/issues/984 Crash in debug mode when placing a "slow cell"
* Bugfix: %GITHUB%/issues/994 Loss of selection when clicking at wrong position
To make this problem less annoying, the capture range was increased when
clicking at already selected items for "Move".
* Bugfix: %GITHUB%/issues/995 New top cell appearing after load
* Enhancement: %GITHUB%/issues/996 Refresh function to trigger update from within library
* Bugfix: %GITHUB%/issues/997 Wrong display of negative extensions of paths
* Bugfix: scale and grids were wrong in case of oversampling

* Bugfix: %GITHUB%/issues/969 PCell error (infinite recursion)

* Enhancement: %GITHUB%/issues/963 Display snapped position in main window
* Bugfix: %GITHUB%/issues/960 Cap values range now shown in netlist browser
* Bugfix: %GITHUB%/issues/954 Fixed a device extraction glitch
* Bugfix: %GITHUB%/issues/951 Internal error fixed when deleting the cell you're sitting at
Side effect: copy & paste of cells is correctly disabled now in viewer mode
* Bugfix: %GITHUB%/issues/942 Technology file routing suffix string typo
* Bugfix: %GITHUB%/issues/946 Python: __file__ returns quoted path string
* Bugfix: DRC check for equal width now returns more consistent results
Previously, a check like "layer.drc(width == something)" was not flagging
all candidates correctly.
* Enhancement: A PCell can request "lazy evaluation" now
This means that a parameter change needs to be committed in the UI before
it is being taken. This way, slow PCell evaluation will not make the
application stall. To add this feature, reimplement "wants_lazy_evaluation"
in the PCell class to return "true".
* Enhancement: "lvs_data" is a global function now in LVS scripts
* Bugfix: less liberal evaluation of expressions in string to numeric conversion
This will fix a potential vulnerability which allows someone to sneak
in expression code through malicious configuration, technology or layer properties
files.

* Enhancements: Better support for execution (also cross-interpreter) of macro code from scripts
- New methods for the Macro class like "run" and loading from file
- New class Interpreter for accessing Ruby interpreter state from Python and vice versa
* Enhancement: New DRC function "enclosed" as the reverse of "enclosing"
- Allows using the rectangle filters with "via enclosed by metal"
- Usually better performance than "metal enclosing via"
* Enhancements: Usability
- Navigation in the 2.5d view
- "tap" function shows layer names and details from layer view
- Documentation about layer views
* Enhancement: CentOS7 RPM's use Python 3 now
* Enhancement: Sending custom query shape objects to RDB produces shape markers now
* Enhancement: New method LayoutViewis_editable?
* Enhancement: %GITHUB%/issues/879 PCellDeclarationlayout and Layoutlibrary ownership links
* Bugfix: %GITHUB%/issues/918 Editor options tab window too big
* Bugfix: %GITHUB%/issues/920 Fill tool border parameter sign issue
* Bugfix: %GITHUB%/issues/921 BJT3 extraction with collector shape fixed
* Bugfix: %GITHUB%/issues/933 QMessageLogger methods safe now with "%" characters
* Bugfix: %GITHUB%/issues/935 Cellinsert (of cell instances) now checks their cell indexes

* Enhancements: Some enhancements on the 2.5d view (e.g. live layer color update, z only scaling, wire frames, etc.)
* Enhancement: simple versions of DRC with_holes/without_holes without parameters
* Enhancement: LVS netlist compare performance improvements in certain cases
* Enhancement: %GITHUB%/issues/914 Make "tap" function available in reader mode
* Bugfix: %GITHUB%/issues/912 Decent error message (not crashing) when trying to create a cell or layer on an empty panel
* Bugfix: %GITHUB%/issues/909 DRC crash
* Bugfix: %GITHUB%/issues/905 Crash when deleting a hierarchical PCell library from Python
* Bugfix: %GITHUB%/issues/898 Spice reader ignores last line
* Bugfix: %GITHUB%/issues/897 Fill Tool crashes
* Bugfix: %GITHUB%/issues/894 border case GDS file behavior restored
* Bugfix: %GITHUB%/issues/892 Font path can be selected for standalone "Basic" library
* Bugfix: %GITHUB%/issues/886 Python module does not build from sources
* Bugfix: %GITHUB%/issues/881 Typo in separation_check signature
* Bugfix: %GITHUB%/issues/880 Clarification of device parameter compare on LVS

* Enhancement: DRC - more filters for edge pair collections
As there are now: with(out)_area and with(out)_internal_angle
* Bugfix: %GITHUB%/issues/846 Crash in netlist browser
* Bugfix: %GITHUB%/issues/851 KLayout stalls in net browser net highlighting when net shapes contain texts
* Bugfix: %GITHUB%/issues/854 Resistor Device extractor extracts W and L 2 times too large
* Bugfix: %GITHUB%/issues/856 LVS: Resistor with bulk: bulk terminal swaps with A terminal
* Bugfix: %GITHUB%/issues/858 "+" line continuation in Spice reader only effective when at beginning of line
* Bugfix: %GITHUB%/issues/859 Technology was not assigned on new layout
* Bugfix: %GITHUB%/issues/864 Shapescopy_shapes does not support undo/redo
* Bugfix: %GITHUB%/issues/866 Probe net not working for floating subcircuits in hierarchical net tracer
* Bugfix: %GITHUB%/issues/867 Macro editor freeze after search next
* Bugfix: %GITHUB%/issues/871 Application stalls with 'draw only border instances' mode with AREFs
* Bugfix: %GITHUB%/issues/875 Drawing glitch
* Enhancement: LVS features
- "extract_devices" returns the device class object
- Device class object can be used to enable parameters (make them primary)
- Spice writer delegate enabled in LVS for customization of output
- "blank_circuit" specifies circuits as black boxes and skips compare
- Better propagation of symmetric nets through swappable pins
- "tolerance" and "join_symmetric_nets" can be used anywhere in the LVS script now
- "same_nets!" (with exclamation mark) for strong matching of nets
- "same_nets" accepts glob pattern now
* Enhancements: RBA/pya
- Devicenet_for_terminal with terminal name
- Circuitnets_by_name with glob pattern
- Netlistis_case_sensitive?, Netlistcase_sensitive=
- Netlistnets_by_name to get nets from pattern
- CellViewcontext_trans and CellViewcontext_dtrans
* Enhancement: Ruby 3.0 basic enabling
* Enhancement: DRC "extent" accepts a cell name pattern now to deliver cell bounding boxes
* Bugfix: reverted change of 796
DXF version is back to AC1006 which seems to be more compatible with most consumers of
DXF files. Using 1016 AC1014 seems to require much more meta information I cannot
provide without deeper insight into the DXF structure.