Peakrdl-regblock

**Updates:**
* Fix oversized address width calculation edge case. 46
* Use sized integer literals in comparisons. 49
* Fix modulo-zero edge case if exporting a block that contains no internal registers. 53

**Updates:**
* Use sized integer literals if bit width exceeds 32-bits. 43

**Updates:**
* Add ability to control default reset style. 34
* Add Intel Avalon MM cpuif. 40
* Add support for field paritycheck. 35
* Fix bug where small designs with 3 or less sw readable addresses, and readback retiming enabled, generate incorrect output.

**Updates:**
* Add support for external components. 4 & 36
* Add support for user defined enums in field encode property. 29
* Add workaround to bug in py3.8/py3.9's distribution metadata discovery. https://github.com/SystemRDL/PeakRDL/issues/16
* Fix issue where write-buffered registers do not accumulate write strobes properly. 38
* Fix edge case where a back-to-back write to write buffer trigger register may get lost.

**Updates:**
* Create output dir prior to export (30, [PeakRDL19](https://github.com/SystemRDL/PeakRDL/issues/19))

**Updates:**
* Rework PeakRDL command-line plugin mechanism.
* Add org cfg schema to allow loading cpuif classes via PeakRDL TOML config.