PyCoRAM 0.9.0 supports both AMBA AXI4 bus and Altera Avalon bus.
Not only master interface (as known as AXI4 master and Avalon master), but also slave interface (as known as AXI4 slave and Avalon slave) is supported. The software executed on a soft-processor (such as Microblaze) can easily accesses in general memory-mapped device manner using volatile variable.
In order to support both Python 3.4 and Python 2.7, AST visiting patterns of Control-thread HLS is modified.
Some new examples on actual FPGAs are added: shortest path search (dijkstra), matrix multiplication, stencil computation, etc.
0.8.0-public
PyCoRAM 0.8.0 is released.
This version includes 2 example accelerator project using PyCoRAM.
- Matrix-matrix Multiplication
- 9-point stencil computation
This version uses Pyverilog 0.7.0 for code parsing and dataflow analysis.
0.7.0-public
PyCoRAM 0.7.0-public with Pyverilog 0.6.0-lite.