Pysystemverilogmodel

**Release created on: 29.09.2021 - 14:16:51**

New Features
* tbd

Changes
* tbd

Bug Fixes
* Added missing `Any` values for `VerilogVersion` and `SystemVerilogversion`.

**Release created on: 28.09.2021 - 21:28:49**

New Features
* None

Changes
* Updated documentation after initial copy&paste from pyVHDLModel.

Bug Fixes
* Fixed copy&paste errors like:
* VHDL → Verilog / SystemVerilog

**Release created on: 25.09.2021 - 20:31:26**

New Features
* Build documentation with BTD.

Changes
* tbd

Bug Fixes
* Fixed URLs due to default branch name `main`.

**Release created on: 25.09.2021 - 17:45:02**

New Features
* Moved classes `VerilogVersion` and `SystemVerilogVersion` from pyEDAA.ProjectModel to this package.

Changes
* None

Bug Fixes
* None