- The `verilogify` can be used to decorate functions for conversion - Additional text-to-text and namespace APIs have also been added
0.1.5
* Previously accidentally built release as module instead of package
0.1.2
* Replaced constants in Verilog with `localparam` * The initialization `ifelse` now runs the previously "first state", reducing clock cycles by 1-2 at all optimization levels
0.1.1
* Patched bug in previous release that caused the optimized graphs to never be used
0.1.0
* `python3 -m python2verilog --help` is the new API * Graph optimizations now utilized by above API, significantly reducing required Verilog clock cycles
0.0.4
* No more nesting of statements * The IR and Verilog both follow a control flow (over the old, nested structure), reducing Verilog clock cycles when optimized