Riscemu

- Feature: Added Zicsr extension and with that support for CSRs
- Feature: Starting to add support for Snitch architecture (Xssr)
- Feature: Add support for `.p2align` assembler directive
- Rework: Improve handling of immediates, so that `beq a0, a1, 1b` and `beq a0, a1, -16` can both can be handled correctly.
- BugFix: Fix some more errors in the RV32F implementation
- Dev: Move to poetry for project development environment
- Dev: Module refactoring, core datastructures now mostly live inside riscemu.core
- Perf: Improved performance by around 1.8x

- Bugfix: Fix some errors in the RV32F implementation (thanks adutilleul)
- Bugfix: Fix how floats are printed in the register view (thanks KGrykiel)
- Bugfix: Fix missing support for infinite registers in load/store ins (thanks superlopuh)

- Added a very basic libc containing a `crt0.s`, and a few functions
such as `malloc`, `rand`, and `memcpy`.
- Added a subset of the `mmap2` syscall (code 192) to allocate new memory
- Refactored the launching code to improve using riscemu from code
- Added an option to start with the provided libc: `-o libc`
- Added floating point support (enabled by default). The RV32F extension is now available

- Added unlimited register mode with `-o unlimited_regs`

- Bugfix: fix a sign issue in instruction parsing for `rd, rs, rs` format
- Bugfix: respect `conf.debug_instruction` setting

- Syscalls: cleaned up formatting and added instructions for extensions
- Parser: fixed error when labels where used outside of sections
- Cleaned up and improved memory dumping code
- Fixed a bug with hex literal recognition in instruction parse code
- Fixed bug where wrong parts of section would be printed in mmu.dump()
- Removed tests for bind_twos_complement as the function is now redundant with the introduction of Int32
- Fixed address translation error for sections without symbols
- Changed verbosity level at which start and end of CPU are printed, added prints for start and stack loading