Add
* Bench against TF, PyTorch, JAX ([5e64152](https://github.com/ashvardanian/SimSIMD/commit/5e64152dc71c94325d0bdf54a282042086847a56))
* Complex dot-products for Rust ([936fe73](https://github.com/ashvardanian/SimSIMD/commit/936fe73349ad0ac0e8523b48e0e35c0142e6252f))
* Double-precision interfaces for JS ([07f2aca](https://github.com/ashvardanian/SimSIMD/commit/07f2acad057132e4a47ca4020173e5b0491b9354))
Docs
* List all APIs ([0a987a3](https://github.com/ashvardanian/SimSIMD/commit/0a987a3ef54d12c0eca8090c4a9507f4a92c9692))
Fix
* Avoid `vld2_f16` on MSVC ([ce9800e](https://github.com/ashvardanian/SimSIMD/commit/ce9800ef9c5d9f811233cc89e7cf2c30b4bff915))
* Complex dispatch in Rust & C ([d349bcd](https://github.com/ashvardanian/SimSIMD/commit/d349bcd20e4b242fd081f6d9ecc944b6b28b23fb))
* Missing `_mm_rsqrt14_ps` in MSVC ([21e30fe](https://github.com/ashvardanian/SimSIMD/commit/21e30febedc5143d21b6e5d5c5ce1cea71d92a95))
* Missing `float16_t` in MSVC Arm64 builds ([94442c3](https://github.com/ashvardanian/SimSIMD/commit/94442c35a3f676983180ea186ab2bae7437ae423))
Improve
* Pragmas for MSVC compatibility ([9d8a8d0](https://github.com/ashvardanian/SimSIMD/commit/9d8a8d070deba1e3bca63137cd96a33347022460)), closes [#74](https://github.com/ashvardanian/SimSIMD/issues/74)
* Silence TF warnings ([0cffc9c](https://github.com/ashvardanian/SimSIMD/commit/0cffc9c294ea08c7a64b15309f582f38e6a71b81))
* Type-casting ([353fe43](https://github.com/ashvardanian/SimSIMD/commit/353fe43244d77b62d9eea73d73353454a2dcfbea))
Make
* 120 line width ([35c1de3](https://github.com/ashvardanian/SimSIMD/commit/35c1de3e0a114104a5466e0756a8632043fe1759))
* Enable SIMD in MSVC builds ([27f24ef](https://github.com/ashvardanian/SimSIMD/commit/27f24ef567eb19127be003168bf7c8e2b4b964de))
* Missing Node & TS dependencies ([9983167](https://github.com/ashvardanian/SimSIMD/commit/9983167b49fb96d5ca419e1fe3216dd967330edd))