Vhdmmio

First usable alpha version. What *should* work is:

- the basic command line for vhdMMIO;
- markdown/mdbook documentation output for vhdMMIO itself;
- HTML documentation output for the generated register files;
- VHDL generation for primitive, interrupt, axi, and custom fields (and their derivatives).

What certainly does not work yet:

- memory fields;
- any kind of logic that is aware of more than one register file at a time (the idea is that register files can be connected hierarchically through AXI fields, and that the documentation and C/Python code for accessing the register files is automatically aware of this);
- C/Python code for accessing the register files (zero effort has been put into this so far).

Changes:

* 0ef939d77c5da0adafbf526e39673bf0e4450fe2 Fix missing template files, autogen MANIFEST.in

This list of changes was [auto generated](https://dev.azure.com/abs-tudelft/vhdmmio/_build/results?buildId=630&view=logs).

NOTE: this release is broken; a couple template files were not included in the distribution. Use 0.0.3 instead.

Changes:

* 33baa91448f16f889aea5ed8b6906ada922c6c44 Commented out memory field config
* e045cc4f569f47b479edef7eaf2f8dd2ef69a456 Add alternative stream monitor example
* 6dcab250ad87b141d1dbb31d0ed5edb786576096 Fix typo in field suffix generation
* 1bbe28764cc064d8892063bbb18f84a61f9502a5 Fix typo in entity template
* fd6e1a0ecec58b4d6a58c1b91d9c1c1582b20bc2 Fix bug in custom field with internals
* ceb290ca0db73800d9a425c0f363c8eda0b23a81 Fix missing end of sentence in documentation
* efd91b3ad718469e44f3e065518d962f13881389 Fix lint errors, implement memory field config
* 389dd1be25e7340c7fa9d021a5093d441a2d0b0a Add flattened bus mode for AXI fields
* 29151b9c15cd9508e2101227aa3ea3df54b3941c Implement AXI fields
* ce8187849a87bc90f77b872051d6f2d4f02f7ea2 Add more tests for deferring fields + bugfixes
<details><summary><b>See more</b></summary>

* 2b228d5f4b2b4c191050bb7ce2d07f99ac7a5694 Add tests for blocking & deferring fields + fixes
* b8cf2f9fb52d9b107061dfed2176d638c9d78b6b Add tests for prot-based security + bugfixes
* 7d51cf8a3fcebf30e75bbfaf1f09f9b74ba26d91 Add additional tests for field repetition
* 7f3dbe775cc993e10841b02210222e19da43e760 Add tests for field repetition + bugfixes
* 5a37596fe75a28ba40b9313faa73d2e06a4a29be Add interface check to all integration tests
* d5cca053ea692e9a7114c088472aabd682118867 Remove unused Parsed config loader
* 23b80bf7895b055ae108e4edd7707a5372f92f90 Add tests for subaddresses + bugfixes
* 8705793fba388e67b43b08b3ca1d5ac1195b2b28 Remove dead VHDL code/TODO
* 89f1e072c275ca6c6385466b6f882bfdbdd50b45 Add test for custom regs with internals + bugfixes
* 12b0acceb4febf138abdc3a8a0633ef19b31a9ca Minor bugfixes
* 70086a91be6e3a6e691842e5f8b8279baed389e9 Add test for custom field state
* ace2b9eaadd6437de0b512f8337659bc84063e1a Save test case VHDL code when vhdeps launch fails
* 0a10c8a30d72d7880a6aecdaa2efa51456478570 Add tests for custom field ports + bugfixes
* e4e67fe10525244e71a35a49feaf44071c19eb6c Add CLI tests for HTML and package generators
* 16574674b07eaae62a9638978bdbde19a7e270a7 Add tests for entity output using CLI + bugfixes
* 475b3336f576a4580460a42f3369e859e8c5ef12 Refactor examples
* 0a33457146f5d2a31da2a1883b05a58a3dcb9d4b Fix bdist_wheel not including all files
* 427824373f927b1111b1b923668df0a2f17a0d89 Clean up
* 1dd7909e09979ee09ee461fef6901ebd283488c1 Fix generated component declaration
* 7231690e1f9dc6ab2f7d0fffbf7a45ff02665d02 Improve config test
* 5b3ecac1d5350d3a25088614e4c6318e3d0cc5c5 Fix cyclic import for version string
* 0720f40a724b160874db01bc09a2994ae04a3092 Print version info in all generated files
* f9fdffa8d88b04f66f8b438876b885be58e07c3b Add entity configuration options
* 7c2f5912b352bc05bf6bc6c85938ede2d1fc42ff Add stream monitor example
* 8db1c340d0f805c08d3608fbbafde14c0cb20181 Add code generation for subaddresses
* 7e2a1504cee577de35cbf2336dcc46b0f3d88c59 Refactor field boilerplate template
* 5714d8732ac96c09f2ee43b128c0407e354d5b5f Add initial tests for custom registers + bugfixes
* 9319ce917cbf5f4e2db2057e364aa06ed49fc120 Implement custom behavior + unrelated bugfixes
* 5900e0eea0a07170191b0a6f4af4cd91e1ecfb3f Define configuration structure for custom behavior
* ba6ea295eda7220a517ef8e8a5b78836e63350a5 Refactor primitive behavior template
* 20321ff4d5c760306d6d208f63f5e0aa5f588fd2 Add tests for stream registers + bugfixes
* f7cc798967e4133a164a59e68c1c8fd9d6c64b37 Add tests for counter registers + bugfixes
* 3a08081fb98b86bd589228b8b5ae5e937842dea7 Add tests for request registers + bugfixes
* 2728a588295fd8c2b4aed5d270bb83f8c700e2d5 Add tests for flag registers + bugfixes
* 30f6e74179b2ab9331795ed8c5668e1f98788e3c Add tests for control registers
* e7607e5f51c87de26e935cb55ebfbf4eb9063dcb Add tests for status registers + bugfixes
* 3478504bf1d4c9802c9de74503580712fb94040a Add tests for constant registers + bugfixes
* ce37ef23cdd87990a7f31fa7b6ae5c07b172e7f2 Add tests for multi-word registers + bugfixes
* 8a6e95b64dbfe7bad6d8d438040d24f85ceec6c4 Add tests for addressing and conditions + bugfixes
* 1313bf4bf4896c4b80b39459ea30c3612de6f87f Add tests for interrupt fields + bugfixes
* 41166c40f2a5360b4298235cad8394a6c7caf6e5 Add tests for interrupt sensitivity + bugfixes
* 38095336258c4378cd5562a0bbfc28c927f10b13 Fix version detection in setup.py
* 78b4ffa94340d82ee730cd350959bdf99f36634c Merge branch 'configuration-cleanup'
* 7dc9e02359e6f8e408ebdf186bce10b27df59540 Update readme slightly
* 89cd0c319a486fbfa8c248b8258b25df86c74fc2 Merge pull request 1 from abs-tudelft/configuration-cleanup
* e823a05345ca8ac5bc58cd46b3d2bfdd22b76e14 Fix CI pipeline
* 327c48253233a450f089454ee813eba4857c62d8 Put stream interface signals in canonical order
* 4522c00e44a7d27548e7abd4305cce1e2bf75321 Add tests for internals
* 305236bd58d2fa3dd15ab9fbd294d4fd616c12e5 Implement VHDL codegen for primitive and interrupt
* 3bde23d5b9b85892f2a2c5ded277ddff85a55b58 Add 'wheel' to setup.py requirements
* d3f50420007088d222419dd733b0e9c8e9995a9e Minor changes to interrupt logic template
* 117a83cb9f1211a7e9278acaa2d237afbaca5f19 Laid foundation for generating field logic again
* 1f9e0996e8e671cb693abcf026ced03696df8621 Complete VHDL generation excluding field logic
* 44c70d2af72183d0eb63e192707515a4993ca4a0 Implement VHDL gen for internals + their I/O
* a3be8428a1621e3a4c90ca4eb3e02e5d4e2efd5e Improve HTML tooltip consistency
* ef6cf5fa6a68f62d756049e0202e8acba9096e0a Store blocks in address manager, expose signal map
* 95f99c25bb63d1f85d111862991e76bb2782a3a1 Add rudimentary way to indent templates
* 5d888c23a41093ddd6d886837d77c44d07a82859 Add option to make internal signals external
* e835e32250f04c893b2f0c5a0976244ecf50411c Fix header levels in generated docs
* ae33aa83b045536208ef52a9358b2d630df6bb75 Add examples, clean up docs
* 5e610f4b17936c561cc1c7973b5d23857f7572cf Refactor test directory
* e75b0144347f80c9d36df858c4b483963259b6cb Reintroduce register file testbench
* 3f33473cd2afae033eff32e1c32ffa4b01768874 Refactor VHDL generator so it doesn't crash
* fab19da46f107ba017671156886bd58c1e143d04 Refactored address decoder code
* 2c1b15350191f6e5419a4681e0874bb4ed3621a2 Add support for overlapping addresses to decoder
* f6d4f6cd58b2cbbf0c57eaa045943f50fb1f4118 Tweaked HTML output
* f13c6d15d74748ff416d7700246a6a1535a0ad7f Fix some unknown keys not detected
* 6db4558fa7ea9cc7eb453ca8742dcbec70bac0a0 Implemented the majority of the HTML generator
* cfe8763c9ef7b86d1e2baba5253c20f6817371d1 Bugfixes, WIP on HTML target
* 3727c77a35bff0688c3db40874d1eda8e89391b7 Improve contextual errors
* e90c0af691ea51840afa601a1a978ad623016be0 Implement interrupts
* 9eba4053832c938f32686fdec65890af0d58c355 Implement registers and blocks
* 0dbb0f55dec93d0f13269f2e7eff18bca5fe0616 Refactor for name consistency
* dde84dcd889b4c01fbda53312550ef3b4d02dc69 Minor fixes/updates
* fee3d5cf516e46fccbadeca1d7d82a45ab6d3223 Modify addressing.py for register builders
* 1562f038b432e8d062eee0c161ac01d3a1d8b524 WIP on behavior code, add primitive
* 64cdf72d16b843ddd4ed46d92694be220230f73a WIP on core
* f515b9e24c4d62903da660c08dfc52060ef59bf0 WIP on core
* e7077ce61d7639310189570472415559478f5770 WIP on core
* 94705f6d2f59314954bcc2e11a8ab4c8ed78e32c Refactor mixins into own module, update AddressMgr
* b32a925545ff3793bb51acd892f4b35428e162b1 WIP on new core code
* bf11388ecf2630b3aaa40500c95374b01d81f6b3 Update mdbook documentation
* f1103c996a5a8466810f070dd98393e6f2ea8ef9 Added configuration keys for advanced addressing
* d303a06ae7a5331efb41c09995481d4578ce0a5e Refactored class names
* bcb024c2302db717998451b1fd99f66bcaabd5fe WIP
* 9bb298a601a19e50ee7e65f0aee4760041c9cefe More refactoring
* f9447d0b05426c311abcbac1dab2d51b1717042f Add basic integration test
* f497d87c8fcebbacd23fe28441bbe5382d6b2d47 Refactor + clean slate: delete all outdated
* 113a02f4adfa846dfac843d0862f8786cf4a430a Re-add load/save API, perform basic tests manually
* 2e9c56ec26eec0dc4880662f11bf0b045377b596 WIP on docs and config file structure
* 8452d18a4688ee843ed47d9cf2b7361dad953cdf WIP on docs and config file structure
* 6aa39de10354d3d3e7fca4cefb6009f7f8c4caa0 WIP on docs and config file structure
* 932b6d811169aac8ca68b9bc7e1c4dfa88d767a6 WIP on config file structure with new system
* cb300c1242d31893eb1d9fd428533f24472683ae Finish mutability/protection of configurables
* 680c98881a27f0e0f58921c31ad32c81569b900f Lots of refactoring in the config system
* 37c6d24b7bd9162c754690473ce10a1572c23ad3 WIP
* 5dfe55d767d31980aea02196a639ba2330b4bc5e Added the last two configuration loaders
* 856900a3b6497dffb65ead39bb097bdeef1f6cfe Refactor configurable code into its own module
* e0b90533bb18bfd12d750d7be1a1fbb2051d13f6 WIP cleaning up configuration code
* a1188c91d4e62cd2729e95a2da7dd49f5657a4c3 WIP cleaning up configuration code
* 553f26b1933922daa4f3e39dbb3e95f8a6373a48 Reorganize field logic submodules
* b3f9d97e97c587d4511ec58fb183e2b281ec0b2d Add .noseids to .gitignore
* 31a051846849cb86fa560b22e7a4738f6a9a7abc Add tests for interrupt fields
* 104e2d9126862765d59f5b2f8743ba4ac0446e72 Improved concepts document
* dbb723d6ff44a4a10086778de837cd4f0efd94f7 Add internal signal support
* 4b7c11a6a5ae25c7c2f86aff7da54024f89cf373 Add tests for flag and counter fields
* c6393c421ea777edbeb137a023586f6f0e3b567a Add more tests for primitive fields
* 464327dbcaeffc51885b1c9b2827286fd01b78d4 Add tests for control registers
* 99ec7b9521f11e93ee1b1e619be418a5a9296849 Add access method flags to ReadWriteCapabilities
* b849608ccec6879b6de7ea264619b72abf6ef0a0 Improve coverage of vhdmmio.vhdl.interface
* 4f90f469c680c068a8ed54b726b208ce2f0b90bb Add tests for metadata objects
* ae8240b5fb9faf0d7ceddda17b01c13c64713838 Improve command line help
* 11903d2b067ae7a3edc1419f241960c9cd9bdbb2 Add badges to README
* 8ba69d513af590a32b525e1856e851af34a8fe04 Refactor test cases, add tests to linter pass
* d54677d28cd987e78fc273a5026c8107c56349c4 Refactor unsecure (not a real word) to non-secure
* e5e6bcb836f8b9536b2e71c15c25fe233b520450 Have nose generate XML coverage and test results
* a78f1f03a50983d80925f299c680e8390d5d29f2 Add automatic version tagging, clean up setup.py
* c04a227589f8958464371495500b5ad74a141e5f Fix lint errors, improve docstrings
* faa143b765fdb48df6f91fe5762bcdb08e61abb6 Add initial azure-pipelines file
* d465faeda4a9394c0399eaae92a6a14f8964943a Rename YAML file used for testing
* 5b0463f9248f7d5e6f1950896193c039f79e3be2 Fix setup.py not installing template files
* edd4d745c64c8a97f452db1857ed99ce3fcd646c Prevent xdg-open from opening py script in browser
* 18366a0c74dbaa3680217c70e55bf6a912b31958 Rethink command-line interface
* 6d8951a336b122a810c2cf8bf0878cda27b0aa5c WIP on docs
* 518132af699fa9b9b2a95e1a3a741a979d7378b0 Add CAPI action register file description
* 027b30a4a2874151295464b0e29669e89f0706c8 Add script entry point to setup.py
* 0ad6498662a659dd942f8bcae58fc2cd8240ce26 Rename AXI field signals for consistency
* 9a6d98aae45788da713daae22080cf6c5cf282e2 Add basic/temporary CLI
* bf1c7cf16fe55675c0c6aa189206a02bdfa58c6a Improve template annotations and error messages
* 5759406f0a7073f6b5ef7a86daaf4ee3fec288f8 Implement initial code for AXI fields
* 8f1e0c2f91e13d3301132d17b26bc622cd432d69 Fix bugs in defer tag generation
* 423f8c2d4c9f036d1b1eb3e78e74c4ce212919ea Update gitignore for Cobertura XML data
* a55a4fe3cd59185b705873a7f7aec8b8f847f305 Add annotations for template coverage
* 40f488ba49c0a685d0317e7c54e2c5d6977a5e40 Add interactive testbench generator for validation
* 3cd2b1c482f271001f41c9bdec32d593e1a3d617 Prepare for AXI passthrough field
* 8568f064f219aaba660374ec600b88348b53338f Add access privileges
* c963012630523a112826bead5e3178ece418da54 Add subfield support
* 4fbe7e42a5aedb44baf3cebbb53e22d5ee212417 Complete interrupt fields
* 6be6fd77e850ab10d9064ce26b5b247131b1f650 Add interrupt fields
* 4d9327e3a7cec611deaf2592040ad0fa706efa18 Add integration test
* c0800a0122b5d698868da30a850bccef0781ca36 Finish templates for primitive fields
* 96db3de04d1fed9762c3ad2fc71db964da286e6f Recreate irq logic and interfaces with new system
* 6aa8d2410c96e651d59820bdf326ac1392605047 Slight cleanup
* 6665567394d00c48dcaddd52e93cde2af9580e61 Complete interface generator
* a8ee60327d0829f3b6563b7a8fdf79f8eb6cce33 WIP
* e65706e3525d71c0f8667b3f39908123dd0bba50 WIP
* 258201035166d6f299ba25132f7b6c38e12805fa WIP
* 3854d22fd46d0a92bb657c67898dffb0f173279c Added VHDL type abstraction layer
* 7ea03185120cbb93105bf649d2d0f2cf94a7d4cf Fixed regression
* 0c91f439e246eceaa3b36e9fcaf2824fc185411b WIP
* 10da5eb542cfc9114d3b046379caaccf4fef5e41 WIP on VHDL generation
* 25f8017856036993c32cf341f0adaa15319d8efb Restructured, tried to pacify linter somewhat
* 9284928a937c0ab1314f7a66e4a07663f097fa8e Finished VHDL address match generator
* e8645bbdef6c37a6239cd3eb16ab7e5a3b622223 WIP
* 093abfcb9152e08def2cccb8c5ee1b1495c8bcd0 WIP
* 11a86401657bce04a789a822323d1c518834587a Fixed VHDL compile errors
* 9721a2b0e5758ad9193b37008b2ed666d4b154c0 WIP on interrupt stuff
* 600bcda1e8f3672dfb2c1a03ebbb2b9be934d91c WIP
* 4f1b2ee54d785e4b6843e1bc46c47ad0352b8a34 WIP
* 2da9b212264835256a424db214f0332472b43822 Finished core for now (no tests yet)
* 96f77c29b58c08820f93f21bc9fb7b4e4ecd83d2 WIP
* 16db13db27494414d6b6c494dba59d1237feefbb WIP on core class hierarchy
* ab11a9599faea4cd0407fd304ab6c981792ddca0 Allow template files to define their own blocks
* c7e2e624081ed040615ce913c4a781e573296254 Apply formatting to all code, not just blocks
* 249c18f4369d998c2ef3186cdc121949e5c52f29 Replace $ comment/wrapping markers with
* bcb8931e81e30a40c2f33a9d32b355c5bce9c625 Allow comment blocks to be indented
* 8d29b73d57b792c2eb94ad080316d3418e8cc794 Minor changes to VHDL template
* e2a885ec2f126ed97f5bff2c6ad84b410b3f0875 Added VHDL code (untested) and a template engine
* 7c1887b23da05719660c433b5c6f54b73c876f14 WIP on toplevel framework
* 407fa0bc1345471b0916fedf2370bc91243a8946 Add brainstorming notes
* 69accba9ae3a41d8820e8918870f54a7f8529434 Add pylint to setup.py
* 6ff3cb20834744382b6b76edca24330f51fa1c4a Add framework for Python tests and code coverage

This list of changes was [auto generated](https://dev.azure.com/abs-tudelft/vhdmmio/_build/results?buildId=628&view=logs).</details>

Initial version for testing purposes. Very little integration testing has been done so far, but what *may* work is:

- the basic command line for vhdMMIO;
- markdown/mdbook documentation output for vhdMMIO itself;
- HTML documentation output for the generated register files;
- VHDL generation for primitive and interrupt fields, plus all the support logic around it. This is the least tested part.

What certainly does not work yet:

- AXI, memory, and custom fields (the necessary subaddress code is also not entirely implemented yet);
- any kind of logic that is aware of more than one register file at a time (the idea is that register files can be connected hierarchically through AXI fields, and that the documentation and C/Python code for accessing the register files is automatically aware of this);
- C/Python code for accessing the register files (zero effort has been put into this so far).