Cocotbext-pcie

Notable changes in this release:

Simulation models:

* Fix IRQ vector min/max range checks
* Properly implement zero-length operations

IP core models:

* Properly implement zero-length operations
* Defer TLP conversion to string when logging
* Implement TLP straddling in Xilinx UltraScale models

Notable changes in this release:

Simulation models:

* Mirror root complex TLP size settings to host bridge
* Transfer configuration from upstream bridge to new switch ports
* New system software abstraction
* Support MSI-X

IP core models:

* Improve PF and MSI configuration
* Properly propagate extended tag support setting
* Add extended tag configuration to Stratix 10 model
* Add max payload size configuration options to device models
* Support MSI-X in device models

Notable changes in this release:

Simulation models:

* Clean up simulation time handling
* Use start_soon instead of fork
* Test on python 3.10
* Fix bridge prefetchable base/limit registers
* Fix config space register region checks

IP core models:

* Log interrupt requests
* Cache clock edge event objects

Notable changes in this release:

Simulation models:

* Logging performance improvements
* Clean up BAR matching and TLP handling
* Include TLP in error logs
* Alias upstream port PCIe ID on PCIe switch
* Use address space abstraction

Notable changes in this release:

IP core models:

* Stratix 10: Fix initial reset level
* Remove deprecated assignments

Notable changes in this release:

IP core models:

- Added PCIe HIP model for Stratix 10 GX/SX/TX/MX H-Tile/L-Tile