Cocotbext-pcie

Notable changes in this release:

Simulation models:

- Added missing returns so that regions with read and write handlers can be read
- Only fix up length field when it is not reserved

IP core models:

- Rework completion error reporting in UltraScale models

Notable changes in this release:

Simulation models:

- Fix register aliasing for secondary status register
- Change log level for TLP routing messages
- Implement parity error and abort status bits
- Split reads on the read completion boundary instead of the max payload size
- Support IO and memory operations of length 0

IP core models:

- Implemented request completed bit in UltraScale TLP object
- Track active requests in UltraScale models
- Report more error conditions in UltraScale models
- Reconstruct lower address field MSBs in UltraScale models
- Report request completed in UltraScale models

This release represents a significant internal overhaul of the PCIe simulation framework. This includes a lot of clean-up, reworking, bug fixes, support for extended capabilities, and initial implementations of the link layer, ACK/NAK protocol, and flow control.

Notable changes in this release:

TLPs:
* Improve TLP typing
* Fix TLP address packing
* Add LN and PH fields to TLP and update tag field to 10 bits
* Ensure TLP payload data is always accessed via get_data and set_data
* Store TLP payload as bytes instead of DWORDs
* Add additional methods for TLP size information
* Change default TLP packer and unpacker to return bytes
* Copy data when copying TLP
* Add sequence number field to TLP
* Add flow control credit release callback to TLP

Link layer:
* Add DLLP object
* Add initial implementation of ACK/NAK protocol
* Add initial implementation of flow control

Capabilities:
* Reorganize capabilities to avoid mixins
* Implement extended capability support
* Add PCIe and AER extended capabilities
* Add enums for capability and extended capability IDs
* Add extended data to MSI capability
* Add additional fields to PCIe capability
* Raise exceptions when requested MSI operations fail

Configuration space:
* Clean up configuration space implementation
* Implement IO space and memory space enable bits

Simulation models:
* Rework device number handling so only bus number is captured
* Add match_tlp and match_secondary_tlp
* Reimplement TLP routing in switch
* Serialize calls to port rx_handler to prevent reordering and re-entering handler
* Add SimPort, convert Port to a generic base class
* Remove port from HostBridge
* Release flow control credits when TLPs are consumed

IP core models:
* Fix UltraScale model handling of sequence number and discontinue signals
* Refactor UltraScale source and sink code to remove drive_frame and to avoid using pop on transmit
* Pass through EP bit in UltraScale models
* Pass link speed and width settings to port in UltraScale models
* Expose flow control state in UltraScale models

Notable changes in this release:

* Limit channel queue depth
* Enforce max queue depth and throw QueueEmpty and QueueFull exceptions in non-blocking operations on streaming interfaces
* Improve transaction ordering on RQ interface (US and US+ PCIe IP core models)

Notable changes in this release:

* Use cocotb async queues

Notable changes in this release:

* Updated for new cocotbext-axi
* Emulate backpressure from completion buffer in ultrascale models