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* Support system-installed Verilator
* Allow tool-specific dependencies
* Allow custom names on synthesis/simulator top levels
* Allow subdirectories in cores_root
* Colorized status output
* Improved exception handling
* Allow verilator test benches to access functions in other cores
* Allow passing options directly to backend tools
* Add preliminary VHDL support
* Integrate Altera Qsys generation in Quartus flow
* Add support for building with Xilinx ISE
* + lots of bug fixes and refactoring
Contributors:
carlos <carlosmarte.inesc-id.pt>
Franck Jullien <franck.julliengmail.com>
Olof Kindgren <olof.kindgrengmail.com>
Stefan Kristiansson <stefan.kristianssonsaunalahti.fi>
Kenneth Lorthioir <ibelimbgmail.com>
Jose T. de Sousa <jtsinesc-id.pt>