Litex

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[> Fixed
--------
- fix SDCard writes.
- fix crt0 .data initialize on SERV/Minerva.
- fix Zynq7000 AXI HP Slave integration.

[> Added
--------
- Wishbone2CSR: Add registered version and use it on system with SDRAM.
- litex_json2dts: Add Mor1kx DTS generation support.
- Build: Add initial Radiant support for NX FPGA family.
- SoC: Allow ROM to be optionally writable (for contents overwrite over UARTBone/Etherbone).
- LiteSDCard: Improve BIOS support.
- UARTBone: Add clock domain support.
- Clocking: Uniformize reset on iCE40PLL/ECP5PLL.
- LiteDRAM: Improve calibration and add BIOS debug commands.
- Clocking: Add initial Ultrascale+ support.
- Sim: Allow dynamic enable/disable of tracing.
- BIOS: Improve memtest and report.
- BIOS: Rename/reorganize commands.
- litex_server: Simplify usage with PCIe and add debug parameter.
- LitePCIe: Add Ultrascale(+) support up to Gen3 X16.
- LiteSATA: Add BIOS/Boot integration.
- Add litex_cli to provides common RemoteClient functions: get identifier, dump regs, etc...
- LiteDRAM: Simplify BIST integration.
- Toolchains/Programmers: Improve checks/error reporting.
- BIOS: add leds command.
- SoC: Do a full reset of the SoC on reboot (not only the CPU).
- Etherbone: Improve efficiency/performance.
- LiteDRAM: Improve DDR4/DDR3 calibration.
- Build: Add initial Oxide support for NX FPGA family.
- Clock/RAM: Reorganize for better modularity.
- SPI-OPI: Various improvements for Betrusted.
- litex_json2dts: Improvements to use it with mor1kx and VexRiscv-SMP.
- Microwatt: Add IRQ support.
- BIOS: Add i2c_scan command.
- Builder: Simplify Documentation generation with --doc args on targets.
- CSR: Add documentation to EventManager registers.
- BIOS: Allow disabling timestamp for reproducible builds.
- Symbiflow: Remove workarounds on targets.
- litex_server: Simplify use on PCIe, allow direct CommXY use in scripts to bypass litex_server.
- Zynq7000: Improve PS7 configuration support (now supporting .xci/preset/dict)
- CV32E40P: Improve OBI efficiency.
- litex_term: Improve upload speed with CRC check enabled, deprecate --no-crc (no longer useful).
- BIOS: Add mem_list command to list available memory and use mem_xy commands on them.
- litex_term: Add Crossover and JTAG_UART support.
- Software: Add minimal bare metal demo app.
- UART: Add Crossover+Bridge support.
- VexRiscv-SMP: Integrate AES support.
- LitePCIe: Allow AXI mastering from FPGA (AXI-Lite and Full).
- mor1kx: Add standard+fpu and linux+fpu variants.

[> Changed
----------
- BIOS: commands have been renamed/reorganized.
- LiteDRAM: rdcmdphase/wrcmdphase no longer exposed.
- CSR: change default csr_data_width from 8 to 32.

---------------------------------------

[> Fixed
--------
- Fix flush_cpu_icache on VexRiscv.
- Fix `.data` section placed in rom (566)

[> Added
--------
- Properly integrate Minerva CPU.
- Add nMigen dependency.
- Pluggable CPUs.
- BIOS history, autocomplete.
- Improve boards's programmers.
- Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
- Speedup Memtest using an LFSR.
- Add LedChaser on boards.
- Improve WishboneBridge.
- Improve Diamond constraints.
- Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
- Add CV32E40P CPU support (ex RI5CY).
- JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
- Add Symbiflow experimental support on Arty.
- Add SDCard (SPI and SD modes) boot from FAT/exFAT filesystems with FatFs.
- Simplify boot with boot.json configuration file.
- Revert to a single crt0 (avoid ctr/xip variants).
- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
- Add AXI-Lite bus standard support.
- Add VexRiscv SMP CPU support.

[> Changed
----------
- Add --build --load arguments to targets.
- Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
- Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
- Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
- Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
- Rename --gateware-toolchain target parameter to --toolchain.
- Integrate Zynq's PS7 as a regular CPU (zynq7000) and deprecate SoCZynq.

----------------------------------------

[> Description
--------------
First release of LiteX and the ecosystem of cores!

LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
Cores/SoCs (with or without CPU).

The common components of a SoC are provided directly:
- Buses and Streams (Wishbone, AXI, Avalon-ST)
- Interconnect
- Common cores (RAM, ROM, Timer, UART, etc...)
- CPU wrappers/integration
- etc...
And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.

It also provides build backends for open-source and vendors toolchains.

[> Fixed
--------
- NA

[> Added
--------
- NA

[> Changed
----------
- https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.