Riscv-config

Fixed
- islegal function under the warl_interpreter class fixed. The based and bound values are not
extracted correctly as either hex or decimal values. Also removed the logic to truncate values

Fixed
- Changed the default value of 'accessible' to false so input yamls need not declare unsupported xlen

Added
- added default-setters for misa's reset value to match the ISA extensions, to modify warl function of extensions under misa
- added default setter for reset value of mstatus
Fixed
- changed default values of types for subfields in mstatus
- changed default values of types for mhpmevent*, mcountinhibit, mcounteren and mhpmcounter* to read only constant 0
- changed default values of types for fflags, frm and fcsr to warl if F is present, else read-only constant 0
- changed default values of types for mcycle[h], minstret[h] to warl
- changed default values of types and added checks for subfields of scause, satp, stvec, sie, sip and sstatus

Fixed
- removed an unadded feature in rv32i_platform.yaml
- removed debug_interrupts under mip in rv64i_isa.yaml

Fixed
- fixed issue 58 by adding extra checks for bitmask
- fixed issue 59 by removing custom cause from platform yaml
- resolved inconsistencies in the use of "xlen" and "supported_xlen" in schemaValidator
Added
- added extra "shadow_type" fields in the csr schemas. These indicate the nature of shadow
(read-only, read-write, etc).
- added parking_loop node in debug_schema to indicate the address of debug rom. Can be empty in
implementations which do not have this feature

Added
- Added checks for K (sub)extension(s)
- Updated docs with information on adding new extension, csrs or specs.
- Added github actions based CI