Skidl

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* Added Network objects to make it easy to create serial & parallel combinations of two-pin parts.
* SKiDL design hierarchy is now embedded in the KiCad netlist that's generated.

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* Added Interface objects for storing complicated sets of I/O signals for subsystems.
* ERC no longer redundantly checks every segment of a multi-segment net and reports multiple errors.
* copy() function of Part, Bus, Pin, Net objects now returns a scalar object while copy(1) returns a list with one object.
* Bus, Pin, and Net objects now have iterators.
* Corrected initialization of KiCad library search paths.

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* Added pull() and fetch() methods for getting/creating existing/new Net and Bus objects.
* Added drive property to pins to override their default pin function attribute.
* Part pins and units can now be accessed as attributes.
* Nets, pins, and buses now support the width property.
* Indexing with brackets now works equivalently for pins, nets, and buses.
* Grouped part pins (such as address and data buses) can now be accessed using a slice-like notation, e.g. memory['ADDR[0:7]'].

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* Matching of pin lists now begins with normal string matching before using regexes.
* Added more tests and fixed existing tests.

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* Selecting part pins now looks for exact match before falling back to regex matching.
* PySpice now needs to be manually installed to perform SPICE simulations.
* SPICE simulations of subcircuits (.SUBCKT) now supported.
* Improvements/additions to the library of supported SPICE parts.

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* SPICE simulations of circuits now supported (Python 3 only).