Spydrnet

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August 14, 2023

* Moved the example netlists and tests out of the python package and added documentation how to use the example netlists
* Updated to use pathlib instead of os
* Added Github actions check to run Pylint and to fail if score is too low
* Added documentation about Pylint and code formatting
* Various minor improvements
* Other small edits to documentation

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April 18, 2023

* Bug fix for Verilog parser for partially connected ports being misaligned and fixed primitive name with a space at the end.
* Changed some of the os.path to pathlib to conform to updated coding standards

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February 2, 2023

* Bug fix for names in EDIF netlists in which they were cut off if more than 100 characters long. Now the allowed number of characters in a name is 255.
* Slight additions to documentation about doing a release
* Removing Travis CI (from now on only Github Actions will do automated testing)
* Fixed bug where architecture liraries were not included in the release

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November 9, 2022

* Major improvements and fixes for the Verilog netlist parser and composer to broaden support and accuracy
* Built in primitive libraries to allow SpyDrNet to populate port directions of primitives when parsing netlist types that don't always explicitly define primitive cells (Verilog, EBLIF). An option is added to parsing to specify which primitive library to use.
* Improvements, fixes, and simplification to EBLIF netlist parser and composer
* Verilog parser and composer option to remove/add lagging space in names
* Documentation updates and improvements

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April 20, 2022

* Bug Fix. Now EBLIF support should actually be included.

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April 9, 2022

* Initial support for parsing and composing EBLIF netlists.