Spydrnet

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April 23, 2021

* included the miniscript to the graph in API summary in the documentation
* added pretty print functions for some Intermediate Representation
* Warning: The Verilog composer is still in progress but works the same as 1.7.0 for now
* Warning: We don't suggest using Python 3.5 for this release. There is an issue with the Verilog parser associated with Python 3.5

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January 21, 2021

* Updated Verilog Parser and Composer to be more generic
* included Tutorial in the documentation
* added some API shortcuts and updated its usage in the documentation

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September 24, 2020

* Fixed minor issue with verilog parser composer access
* Update Documentation and its organization

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September 1, 2020

* Verilog Parser
* Verilog Composer

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April 21, 2020

* Flattening functionality
* Bug fixes

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March 19, 2020

This is a major functionality wise release.

* Added Hierarchical references
* Added clone functionality
* Added whole netlist uniquify ability
* Updated/Fixed the composer and parser to use the new element[".NAME"] feature
* Updated/Fixed the namespace manager to allow for multiple netlists in a session
* Updated callback framework to autoregister implemented functions.
* Added verilog tokenizer based on ``ply``
* Added tcl scripts for converting EDIF netlist to Verilog using Vivado
* Added powerful getter functions and shortcuts to ease naviation of the nextlist
* Updated examples and documentation