* Add UNUSED error message, for forward compatibility.
3.521
===============================
**Major:**
* Create new --coverage-line and --coverage-user options. [Peter Holmes]
**Minor:**
* Add SystemVerilog 'x,'z,'0,'1, and new string literals. * Fix public module's parent still getting inlined.
3.520
=================================
**Major:**
* Support $fopen, $fclose, $fwrite, $fdisplay. See documentation, as the file descriptors differ from the standard.
3.510
=================================
**Major:**
* Improve trace-on performance on large multi-clock designs by 2x or more. This adds a small ~2% performance penalty if traces are compiled in, but not turned on. For best non-tracing performance, do not use --trace.
**Minor:**
* Fix $'s in specify delays causing bad PLI errors. [Mat Zeno] * Fix public functions not setting up proper symbol table. [Mat Zeno] * Fix genvars generating trace compile errors. [Mat Zeno] * Fix VL_MULS_WWW compile error with MSVC++. [Wim Michiels]
3.502
=================================
**Minor:**
* Fix local non-IO variables in public functions and tasks. * Fix bad lifetime optimization when same signal is assigned multiple times in both branch of an if. [Danny Ding]
3.501
=================================
**Major:**
* Add --prof-cfuncs for correlating profiles back to Verilog.
**Minor:**
* Fix functions where regs are declared before inputs. [Danny Ding] * Fix bad deep expressions with bit-selects and rotate. [Prabhat Gupta]