Rapidwright

**Notes:**
- API Additions:
- com.xilinx.rapidwright.design.SiteInst "public boolean unrouteIntraSiteNet(BELPin src, BELPin snk)"
- com.xilinx.rapidwright.design.SitePinInst "public void setSiteInst(SiteInst instance, boolean keepRouting"
- com.xilinx.rapidwright.device.Wire "public ArrayList<PIP> getBackwardPIPs()"
- com.xilinx.rapidwright.device.Wire "public ArrayList<PIP> getForwardPIPs()"
- API Removals:
- com.xilinx.rapidwright.device.Wire "public ? getBackwardPIPs()"
- com.xilinx.rapidwright.device.Wire "public ? getForwardPIPs()"
- Resolves issues: 14, 15
**Known Issues:**
- Netlists that have two ports by same name where one is a single bit
bus and another is multi-bit are not currently supported (for
example, a module has an input 'my_signal' and 'my_signal[2:0]' is
currently not allowed in the EDIF parser.
- Clock router in Router class is disabled (under development).
- PolynomialGenerator is a toy demonstration and does not produce a
functionally valid circuit.

**NOTE: rapidwright_data.zip has not changed since 2018.2.0 and is not required to be re-downloaded to update.**

**Notes:**
- API Additions:
- com.xilinx.rapidwright.design.Design "public Cell createAndPlaceIOB(String name, PinType dir, String pkgPin, String ioStandard, Net portNet, EDIFNet logNet)"
- com.xilinx.rapidwright.design.Design "public Cell placeIOB(EDIFCellInst bufInst, String pkgPin, String ioStandard)"
- API Removals:
- com.xilinx.rapidwright.design.Design "public EDIFCellInst createIBUF(String portName, Site site, Net portNet, EDIFNet logNet, String ioStandard)"
- com.xilinx.rapidwright.design.Design "public Cell createOBUF(String portName, Site site, Net portNet, EDIFNet logNet, String ioStandard)"

- Enables fix to run HandPlacer in both modes of BlockStitcher (rapid_compile_ipi)
- Fixes routing issue when loading two different devices
- Fixes some issues related to creating top-level ports
- Removes artificial anchor for Modules that do not have internal logic (anchor is allowed to be null)
- Resolves issue: 8
**Known Issues:**
- Netlists that have two ports by same name where one is a single bit
bus and another is multi-bit are not currently supported (for
example, a module has an input 'my_signal' and 'my_signal[2:0]' is
currently not allowed in the EDIF parser.
- Clock router in Router class is disabled (under development).
- PolynomialGenerator is a toy demonstration and does not produce a
functionally valid circuit.

**NOTE: rapidwright_data.zip has not changed since 2018.2.0 and is not required to be re-downloaded to update.**

**Notes:**
- API Additions:
- com.xilinx.rapidwright.device.PIP "public boolean isRouteThru()"
- com.xilinx.rapidwright.device.Site "public BEL[] getBELs()"
- com.xilinx.rapidwright.design.SiteInst "public BEL[] getBELs()"
- com.xilinx.rapidwright.design.SiteInst "public String getPrimarySitePinName(String alternateSitePinName)"
- com.xilinx.rapidwright.design.SiteInst "public String getAlternateSitePinName(String primarySitePinName)"
- com.xilinx.rapidwright.design.Module "public PBlock getPBlock()"
- com.xilinx.rapidwright.design.Module "public void setPBlock(PBlock pblock)"
- com.xilinx.rapidwright.design.Module "public Map<String, String> getMetaDataMap()"
- com.xilinx.rapidwright.design.Module "public void setMetaDataMap(HashMap<String, String> metaDataMap)"

- API Removals:
- com.xilinx.rapidwright.design.Module "public String[] getExternalInputNames()"
- com.xilinx.rapidwright.design.Module "public void setExternalInputNames(String[] externalInputNames)"
- com.xilinx.rapidwright.design.Module "public String[] getExternalOutputNames()"
- com.xilinx.rapidwright.design.Module "public void setExternalOutputNames(String[] externalOutputNames)"
- com.xilinx.rapidwright.design.Module "public HashMap<String, ArrayList<String>> getMetaDataMap()"
- com.xilinx.rapidwright.design.Module "public void setMetaDataMap(HashMap<String, ArrayList<String>> metaDataMap)"

- API Renames:
- com.xilinx.rapidwright.design.Module "public String getPBlock()" --> "public String getPBlockString()"
- Changes Implementation Guide File extension from '.impl.guide' to '.igf'
- Fixed an issue in the HandPlacer where it would fail to start because of some missing saveDesign() methods.
- Modules now store PBlocks when using the rapid_compile_ipi flow
- If no impl guide file is supplied, rapid_compile_ipi will create an example file
- enables non-LUT routethrus in Router
- Resolves issue: 7

**Known Issues:**
- Netlists that have two ports by same name where one is a single bit
bus and another is multi-bit are not currently supported (for
example, a module has an input 'my_signal' and 'my_signal[2:0]' is
currently not allowed in the EDIF parser.
- Clock router in Router class is disabled (under development).
- PolynomialGenerator is a toy demonstration and does not produce a
functionally valid circuit.

**NOTE: rapidwright_data.zip has not changed since 2018.2.0 and is not required to be re-downloaded to update.**

Notes:
- API Additions:
- com.xilinx.rapidwright.device.Site "public SiteTypeEnum[] getAlternateSiteTypeEnums()"
- com.xilinx.rapidwright.design.SiteInst "public SiteTypeEnum getPrimarySiteTypeEnum()"
- com.xilinx.rapidwright.design.SiteInst "public SiteTypeEnum[] getAlternateSiteTypeEnums()"
- API Removals:
- com.xilinx.rapidwright.device.Site "public SiteType getPrimarySiteType()"
- Resolves issues: 5, 6
- Preliminary tutorial for running IP Integrator flow (rapid_compile_ipi)
Known Issues:
- Netlists that have two ports by same name where one is a single bit
bus and another is multi-bit are not currently supported (for
example, a module has an input 'my_signal' and 'my_signal[2:0]' is
currently not allowed in the EDIF parser.
- Clock router in Router class is disabled (under development).
- PolynomialGenerator is a toy demonstration and does not produce a
functionally valid circuit.
- Issue 4 - JDK9 Compliance for some 3rd party libraries prints out warnings

**NOTE: rapidwright_data.zip has not changed since 2018.2.0 and is not required to be re-downloaded to update.**

Notes:
- Initial release with new RapidWright API Library
Known Issues:
- Netlists that have two ports by same name where one is a single bit
bus and another is multi-bit are not currently supported (for
example, a module has an input 'my_signal' and 'my_signal[2:0]' is
currently not allowed in the EDIF parser.
- Clock router in Router class is disabled (under development).
- PolynomialGenerator is a toy demonstration and does not produce a
functionally valid circuit.
- Issue 4 - JDK9 Compliance for some 3rd party libraries prints out warnings