Rapidwright

**Release Notes:**
- Shell creation improvements to enable lock_design and timing closure preservation (760)
- Adds a MakeBlackBox command line tool (747)
- Removes the VCC A6 pin on 5LUT usages when removing cells (741)
- Add DesignTools.getAllRoutedSitePinsFromPhysicalPin() (755)
- Correctly update dual-output route flags when unrouting (737)
- [PhysNetlistReader] Set cell type of LOCKED cells (767)
- Updates RAM32X1S property to correct default (751)
- [Interchange] PhysNetlistReader to create STATIC_SOURCE SiteInsts (766)
- RWRoute Fixes (765)
- GlobalSignalRouting.routeStaticNet() to create output SPIs (761)
- DesignTools.createCeSrRstPinsToVCC() to skip non-SLICE FFs (744)
- [PartialRouter] Improve incremental global routing (759)
- GlobalSignalRouting fixes for routing to non clock-pins (757)
- DesignTools.makePhysNetNamesConsistent() to merge static nets too (753)
- [UltraScaleClockRouting] Reset RouteNode.parent (752)
- Created parameterizable counter with an adder as a submodule (713)
- [RWRoute] Fix PartialRouter for when clk node already unpreserved (746)
- [Interchange] Fix PhysicalNetlist's MultiCellPinMapping (743)
- Unroute site routing when removing a cell (729)
- PartialRouter's global router to not unpreserve sink nodes (736)
- DesignTools.makePhysNetNamesConsistent() to use hier name (735)
- DesignTools.makePhysNetNamesConsistent() to consider */<const{0,1}> (734)
- Add DcpToInterchange class (704)
- Add compile step (733)
- Add EdifToLogicalNetlist to MainEntrypoint (731)
- Fix Javadoc warnings (723)
- Fixes an issue with makeBlackBox trying to remove pins from renamed nets (728)
- [PhysNetlistReader] Set Cell type for routethru cells (727)
- Multilevel macro expansion (726)
- TestReplaceEDIFInDCP to copy DCP before replacing in-place (725)
- DesignTools.createMissingSitePinInsts() to skip node-less site pins (724)
- Fix to create alternate source pins on dual output nets.
- Fixes incorrect Versal SLR corner tile entries
- Cell.getProperty() returns null if no EDIFCellInst found
- Cell.getAllSitePinsFromLogicalPin() to not return any null pins
- Cell.getAllCorrespondingSitePinNames() to not NPE if no physical pin mapping
- Cell.getCorrespondingSitePinName() to consider F?MUX routethrus
- API Additions:
- com.xilinx.rapidwright.device.PIP "public boolean isLogicalDriver()"
- com.xilinx.rapidwright.design.Cell "public String getCorrespondingSitePinName(String logicalPinName, String physPinName, List<String> siteWires)"

**Release Notes:**
- UltraScale Incremental Clock Router Improvements (540)
- Adds VivadoTools, a Vivado wrapper/helper in RapidWright (684)
- Fixes published Maven Central jar (698)
- Enhancements to RWRoute (691, 696)
- Interchange reader/writer improvements (677)
- Fix for issue 709
- Improves handling of site routing and site pins when updating
physical netlist

**Release Notes:**

- Support for Vivado 2023.1 devices and reading 2023.1 DCPs
- Full adoption of Zstandard compression for all device and data
files - 11% faster device loads and 108% faster device cache loads with file size reductions of 32% and 52% respectively.
- Has a new 'rapidwright' run wrapper that avoids the need to set CLASSPATH, provides convenience to run any class file with a main() method, run the Jython interpreter and enables one-liner Jython commands. Run `rapidwright` at the prompt for more details.
- Fix duplicate net source pins (won't set the alternate source if it is the same as the source)
- Change Net.connect() behavior to connect to existing SitePinInst if net is null
- DesignTools.createCeSrRstPinsToVCC() to detect gnd to invert (664)
- EDIFNetlist.cellInstIOStandardFallback to collect set of IOSTANDARDs instead of throwing an error if there is a conflict (671)
- [EDIF] More expanded macros to be deep copied from prim library (672)
- Ignore TestCheckOpenFilesInstalled.test if outside of gradle (674)
- [EDIF] EDIFNetlist.collapseMacroUnisims() to not clobber cell (675)
- [EDIF] Explicit DEFAULT IOStandard on Cell to be overriden by Net (686)
- API Additions:
- (None)

- API Deprecation Removals (--> Replacements) [Closed Source]:
- com.xilinx.rapidwright.device.Tile "public String getNameRoot() --> "public string getRootName()"
- com.xilinx.rapidwright.device.Device "public Tile[][] getTilesByNameRoot(String nameRoot)" --> "getTilesByRootName(String rootName)"

**NOTE:** Due to GitHub size limitations, All Series7 devices are now located in `rapidwright_data2.zip`. All other files are in `rapidwright_data.zip`.

**Release Notes:**
- Adds preliminary support for Zstandard compression. Uses it in device cache file generation. Next release will use it for all data files.
- Fixes an issue with missing Versal Premium families unisim data (631)
- Adds an option to the Interchange device model writer to exclude routing info. to enable placement of the largest devices (658)
- Fixes an issue in the PBlockGenerator parser (633)
- Resolves an issue where collapsed macro ports' parent reference was not set properly (654)
- EDIFNetlist.getIOStandard() to inherit IOStandard from EDIFNet (646)

- API Additions:
- com.xilinx.rapidwright.design.Design "public static boolean readEdifAndXdefInParallel()"
- com.xilinx.rapidwright.design.Design "public static void setReadEdifAndXdefInParallel(boolean readEdifAndXdefInParallel)"

**NOTE:** Due to GitHub size limitations, All Series7 devices are now located in `rapidwright_data2.zip`. All other files are in `rapidwright_data.zip`.

**Release Notes:**
- Includes new API to ensure all downloaded/generated dependant files are present in RapidWright install (613)
- Change in Cell.hashCode() and Cell.equals() behavior such that it now distinguishes routethru cells (624), see Issue 611
- Fixes an issue with isFF() (622)
- Resolves issue with Cells and Nets that contain backslashes not being properly loaded (612)
- Fix for parsing gzipped EDIF files in parallel (619)
- Fix for EDIF export bussed names that collide with bitty names (616)

- API Additions:
- com.xilinx.rapidwright.device.Device "public void ensureDeviceCacheFileIsGenerated()"

**NOTE:** Due to GitHub size limitations, All Series7 devices are now located in `rapidwright_data2.zip`. All other files are in `rapidwright_data.zip`.

**Release Notes:**
- Preserves hwdef information in DCP (597)
- Adds APIs to access BELAttr information in design (598)
- Many improvements to RWRoute to cleanup code and improves both quality and runtime performance
- Fixes a bug with 2022.2 DCPs where hierarchical names were getting mangled in RapidWright (603)
- Adds support for reading gzipped EDIF files
- Fixes an issue with Design.updateDesignWithCheckpointPlaceAndRoute() on more recent version DCPs (601)

- API Additions:
- com.xilinx.rapidwright.design.Design "public Map<Site, SiteConfig> getBELAttrs()"
- com.xilinx.rapidwright.design.Design "public BELAttr addBELAttr(Net net, Site site, SiteTypeEnum type, BEL bel, String name, String value)"
- com.xilinx.rapidwright.device.Device "public BEL getBEL(SiteTypeEnum type, String belName)"
- com.xilinx.rapidwright.device.Device "public BEL[] getBELs(SiteTypeEnum type)"