Rapidwright

**Release Notes:**
* Adds initial support for Versal devices (Vivado 2020.2 compatibility)
* Augments PackagePin metadata to more closely provide available properties found in Vivado.
* To support interchange: DesignTools.getInvertiblePinMap() which provides a map for a unisim to
denote which pins are invertible by which parameter names
* The Part class has been augmented with a set of new methods that contain basic resources
for a particular part that are reported in Vivado with the 'report_property' command,
these methods include: getAvailableIobs(), getBlockRams(), getDsp(), getFlipflops(),
getGbTransceivers(), getLutElements(), p.getMmcm() and p.getUltraRams()
- API Additions:
- com.xilinx.rapidwright.design.Net "public boolean setBufferDelay(Site site, int value)"
- com.xilinx.rapidwright.design.Net "public boolean getBufferDelay(Site site)"
- com.xilinx.rapidwright.device.BEL "public BELPin getInvertingPin()"
- com.xilinx.rapidwright.device.BEL "public BELPin getNonInvertingPin()"
- com.xilinx.rapidwright.device.PackagePin "public boolean isGeneralPurpose()"
- com.xilinx.rapidwright.device.PackagePin "public boolean isGlobalClk()"
- com.xilinx.rapidwright.device.PackagePin "public boolean isLowCap()"
- com.xilinx.rapidwright.device.PackagePin "public boolean isVrn()"
- com.xilinx.rapidwright.device.PackagePin "public boolean isVrp()"
- com.xilinx.rapidwright.device.PackagePin "public boolean isVref()"
- com.xilinx.rapidwright.device.Site "public boolean isGlobalClkPad()"
- com.xilinx.rapidwright.device.Site "public boolean isGlobalClkBuffer()"
- com.xilinx.rapidwright.device.Site "public boolean isRegionalClkPad()"
- com.xilinx.rapidwright.device.Site "public boolean isRegionalClkBuffer()"
- API Deprecations:
- com.xilinx.rapidwright.device.Package "public String getSiteType(String packagePinName)"
- com.xilinx.rapidwright.device.PackagePin "public String getSiteType()"
- API Removals (deprecated):

**Release Notes:**
* Fixes Issue 110 - Bad index because of integer overflow in VU19P.
* Fixes other issues related to logical -> physical mappings
* Fixes other issue related to Issue 63 in Wire.getStartWire()
* Updates EDIFTools.connectLogicalNetAcrossHierarchy() to update
parent net map.
- API Additions:
- com.xilinx.rapidwright.design.Cell "public BELPin getBELPin(EDIFHierPortInst p)"
- com.xilinx.rapidwright.design.Cell "public BELPin getBELPin(EDIFPortInst p)"

**Release Notes:**
* Fixes Issue 104 - NPE for Node.isTied() issue.
* Fixes Issue 105 (and Issue 63) - NPE and missing Nodes for Wire.getNode()
* As part of the fix for 105/63, a Node cache is constructed behind
the API for the first call to an uncommon wire object.
* Deprecates all Node constructors and replaces with a Node.getNode()
equivalent also adds a sentinel "Invalid" Node for bad nodes on construction.
- API Additions:
- com.xilinx.rapidwright.device.BEL "public boolean isGndSource()"
- com.xilinx.rapidwright.device.BEL "public boolean isVccSource()"
- com.xilinx.rapidwright.device.BEL "public boolean canInvert()"
- com.xilinx.rapidwright.device.Node "public Node getNode(RouteNode routeNode)"
- com.xilinx.rapidwright.device.Node "public Node getNode(Tile tile, int wire)"
- com.xilinx.rapidwright.device.Node "public Node getNode(Wire wire)"
- com.xilinx.rapidwright.device.Node "public Node getNode(Tile tile, String wireName)"
- com.xilinx.rapidwright.device.Node "public Node getNode(String nodeName, Device dev)"
- com.xilinx.rapidwright.device.Node "public boolean isInvalidNode()"
- com.xilinx.rapidwright.device.Node "public IntentCode getIntentCode()"
- com.xilinx.rapidwright.device.Node "public IntentCode hasIntentCode(IntentCode intentCode)"
- API Modifications:
- com.xilinx.rapidwright.design.Cell "public Map<String,String> getPinMappingsL2P()"
--> Changed return type: "public Map<String,Set<String>> getPinMappingsL2P()"
- com.xilinx.rapidwright.design.Cell "public List<String> getAllPhysicalPinMappings(String logicalPin)"
--> Changed return type: "public Set<String> getAllPhysicalPinMappings(String logicalPin)"
- API Deprecations:
- com.xilinx.rapidwright.device.Node "public Node(RouteNode routeNode)"
- com.xilinx.rapidwright.device.Node "public Node(Tile tile,int wire)"
- com.xilinx.rapidwright.device.Node "public Node(Wire wire)"
- com.xilinx.rapidwright.device.Node "public Node(Tile tile, String wireName)"
- com.xilinx.rapidwright.device.Node "public Node(String nodeName, Device dev)"

**Release Notes:**
* Fixes a bug with incorrect SRL16* pin mappings on Series 7 and
STARTUPE3 pins on Zynq UltraScale+
* Checks for null parameters on Design.placeCell() - See Issue 91
* Removes incorrect board reference from DCPs created in RapidWright
* Fixes an issue with Cell -> BEL pin mappings where parameters don't
have entries
* Switches to GitHub Actions from Travis CI for automatic builds
* Changes default behavior for Kryo so that it no longer requires
class registering
- API Additions:
- com.xilinx.rapidwright.design.Design "public static EDIFLibrary getPrimitivesLibrary(String deviceName)"

**Release Notes:**
* Adds 2020.1 update 1 Vivado devices (XCVU19P, XCZU46DR, XCZU47DR,
XCZU48DR, XCZU49DR; Alveo devices: U55N, U55C)
* Adds a netlist flattening helper method ()
* Adds preliminary support for reproducing intermediate clock routing
state through the use of partial PIPs - not necessarily modifiable
though. This is intermediate routing information added to clock nets
after during place_design that informs clock routing during
route_design. Previously this was causing some ERRORs when writing
out placed DCPs.
* Some PIPs in these intermediate clock nets can have PIPs with no
end wire. This can be checked with PIP.isEndWireNull(). Or
compare the end wire index with PIP.NULL_END_WIRE_IDX (0x0000FFFF).
* Various netlist helper methods (see commit log for details).
- API Additions:
- com.xilinx.rapidwright.design.Net "public boolean hasGapRouting()"
- com.xilinx.rapidwright.design.Net "public void setHasGapRouting(boolean hasGapRouting)"
- com.xilinx.rapidwright.design.SitePinInst public Integer getSiteWireIndex()
- com.xilinx.rapidwright.design.SitePinInst public Integer getSiteWireName()
- com.xilinx.rapidwright.design.SitePinInst public Integer getSiteWireBELPins()
- com.xilinx.rapidwright.device.PIP "public boolean isEndWireNull()"

**Release Notes:**
* Re-adds missing macro primitive definitions that were absent in previous releases
* Adds missing macro/translated primitive definitions IOBUFDS and OBUFTDS_DUAL_BUF
* Adds some basic helper methods to handle route-thrus
* Adds APIs to provide default property values for primitive cells (often unisims)
* Minor update with API additions
- API Additions:
- com.xilinx.rapidwright.design.SiteInst "public void unrouteSite()"
- com.xilinx.rapidwright.design.Design "public static EDIFLibrary getPrimitivesLibrary()"
- com.xilinx.rapidwright.design.Design "public static VivadoProp getDefaultProperty(Series series, String cellTypeName, String propName)"
- com.xilinx.rapidwright.design.Design "public static Map<String, VivadoProp> getDefaultCellProperties(Series series, String cellTypeName)"