Siliconcompiler

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**Minor:**

* Added helper function to allow tasks to handle clock information in a uniform method.
* Improved feedback on unsupported platforms during `sc-install`.


* Tools:

* bambu: updates to better handle platform and clock information.
* openroad: added recover_power option support.
* yosys: switch to use builtin `keep_hierarchy` to speedup compile times.

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**Major:**

* Added color support to logger to allow for easier identification of warnings and errors.

**Minor:**

* Corrected install scripts for surelog and bambu.
* Fixed task setup order to avoid setting up tasks before the input nodes have been setup.

* Tools:

* slang: added elaboration task.
* yosys: added controls for separator used during flattening via `['tool', 'yosys', 'task', 'syn_asic', 'var', 'hierarchy_separator']`.

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**Major:**

* Added gtkwave show task to allow for vcd viewing.
* Removed enablement for conda-eda as this is no longer a supported project.

**Minor:**

* Allow passing a file path to `.register_source` to make it easier to handle retive path to the current file.

* Tools:

* openroad: added support for mutli-bit flipflop mapping and initial support for scan chain insertion, correct pin ordering from constraints.

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**Major:**

* Added optional `optimizer` install extra to provide design optimization via google-vizier.

**Minor:**

* Added capability to import flist files via `Chip.import_flist`
* Added quiet loglevel to limit siliconcompiler logging to just the most critical information.

* Tools:

* openroad: switch to turn on new macro placer by default and correct handling of dont_use based on cell lists.
* yosys: add detailed metrics for cell counts, added support for handling clockgate insertion, simplified library file handling, and updated lec task.
* sta: added check_library task to help verify library setups for asic flows.

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**Major:**

* Update asicflow and openroad driver to utilize smaller tasks. This is a breaking change from the previous implementation, but allows for better flow composability.
* Added `['record', 'pythonversion']` and `['record', 'pythonpackage']` to schema to allow to better environment and provenance tracking.


**Minor:**

* Reworked remote client into single class to allow for better job tracking locally.
* Updated logic for printing package access information to avoid repeating information when possible during a run.

* Tools:

* openroad: rework tasks into smaller tasks, add access to `eliminate_dead_logic` via `['tool', 'openroad', 'task', 'init_floorplan', 'var', 'remove_dead_logic']`
* yosys: fix fpga synthesis to allow for better macro extraction and added ability to map tri-state buffers to asic synthesis.

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**Minor:**

* Added option to limit size of emailed logs based on number of lines.
* Fixed handling of `find_files` in frontend tools
* Removed automatic error when FPGA is not loaded, as this can be handled by the tool/task drivers.

* Tools:

* vivado: update tool and task drivers to handle v2024.x and cleaned up output filenames.