Siliconcompiler

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0.26.4

=========================================

**Minor:**

* Limit schema sections getting imported from libraries to speed up importing.
* Added verilator tool option to dvflow.
* General speedup improvements to schema object.
* Added `find_node_file` helper function to make accessing files in the node run directory as easy as possible.

0.26.3

=========================================

**Major:**

* Removed `-generate` from `sc-issue` when creating a sharable testcase.
* Allow for recursive definitions of asic logic and macro libs from imported libraries.

**Minor:**

* `smake` improved handling of boolean arguments and arguments with default values.
* Corrected `.swap_library` to correctly swap libraries.

0.26.2

=========================================

**Minor:**

* Added portname to pins in schema.
* Allow `.swap_library` to swap to `None` when removing a soft-library.

* Tools:

* openroad: fixed max density error to 100% and allow for multiple padring files to be loaded instead of just one.

0.26.1

=========================================

**Major:**

* Added `smake` commandline tool to enable a Makefile like interface to `make.py` files.
* Removed the need to have local execution for remote jobs.

**Minor:**

* Added additional helper functionality to `Library`, `PDK`, and `FPGA` to better handle package registration.

0.26.0

=========================================

**Major:**

* Removed ['option', 'copyall'] from schema.
* Updated ['option', 'loglevel'] to be lower case settings.
* Added ['record', 'toolexitcode] to track the tool exit code during execution.
* Added whitelist of directories to `sc-remote` to avoid uploaded directories not approved by the user.
* Add support to automatically add soft IP libraries to ['option', 'library'] if specified by the library developer.

0.25.0

=========================================

**Major:**

* Removed ['option', 'mode'] and ['option', 'frontend'] from schema.
* Moved flowgraph runtime information into ['record', ...].
* Implemented a dynamic flowgraph that is capable to skipping nodes that are not needed, for example in the case that a design contains VHDL and not verilog, the verilog preprocessing is skipped.
* Split ['input', 'rtl', 'verilog'] into ['input', 'rtl', 'systemverilog'] and ['input', 'rtl', 'verilog'] to be better able to tell the file types apart.
* Added support for remote jobs to be marked as rejected.


**Minor:**

* Fixed issue generation for python only tasks.
* Added memory usage collection to python only tasks.
* Prevent `Chip.collect()` from collecting the user home directory and current build directory.

* Tools:

* slang: added warning and error metrics collection.

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