Siliconcompiler

Latest version: v0.23.3

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0.21.0

Not secure
=========================================

**Major:**

* Added support for handling soft libraries in the schema via ['option', 'library'] and updated all frontend task drivers to support these.

**Minor:**

* Ensure that libraries, which import a library, are handled correctly.

0.20.3

Not secure
=========================================

**Minor:**

* Added testing to ensure command line arguments are all checked for functionality and follow the schema pattern.
* Fixed python package lookup when the installed package does not match the name of the distribution.
* Added print controls to command line applications to allow custom arguments to be displayed along with schema values via the key `sc_print:`.
* Updated the conda environment and added testing to ensure functionality.

0.20.2

Not secure
=========================================

**Minor:**

* Fixed some issued identified by tclint.
* Added helper function to better detect locally installed and editable python packages for package registration.

0.20.1

Not secure
=========================================

**Major:**

* Moved from hosting third party pdks in SiliconCompiler to fully using lamdapdk.
* Added a demonstration target for gf180.

**Minor:**

* Tools:

* vpr: added support for pin constraints.
* openroad: added estimated routing congestion to the task image writing and updated fmax metric collection to use OpenROAD directly.

0.20.0

Not secure
=========================================

**Major:**

* Update file path hashing to include package information.

**Minor:**

* Tools:

* yosys: update FPGA synthesis to better map LUTs and memories.
* openroad: added option to control CTS with obstruction awareness via via ['tool', 'openroad', 'task', 'cts', 'var', 'cts_obstruction_aware'].
* klayout: added operation to be able to rename cells in layout via ['tool', 'klayout', 'task', 'operations', 'var', 'operations', 'rename_cell'].

0.19.1

Not secure
=========================================

**Major:**

* Tools:

* yosys: updated implementation for FPGA flow to better support flip-flop mapping and hard macro extraction and mapping.

**Minor:**

* Package downloading to ensure GitHub release artifacts can be downloaded from private repositories.

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