Kratos

Added
- Add default output value for FSM
- Add pass to fix port legality (off by default)

Changed
- Unique case now has default to handle x warning in simulator
- Update hgdb schema

Fixed
- Minor fix on variable shadowing
- Fix size-1 FSM
- Fix decouple ports missing ternary op cond

Added
- Add hgdb data breakpoint support
- Add support for skipping auto clock gating (168)
- Improve packed struct (may not be backwards compatible)

Fixed
- Fix new width calculation

Added
- Accept `DEBUG` env when building python wheels
- Add support for child interface wiring in syntax sugar
- More C++ API exposed to Python
- Add big num supports to constants

Changed
- pybind and google test udpated. Should not affect front end
- Throws exception is nullptr is used for assignment
- Case statement now uses the actual constant value
- Better Verilog port parsing

Fixed
- Fix width param calculation
- Fix interface connect scoping issue
- Fix wiring merging on different size (165)
- Fix return type for imported generator
- Fix CXX ABI due to linc linking

Added
- Event support for debugging. Events are specialized logic that can be used in HGDB
- Add pass that can automatically lift instance array into genvar construct (162)

Changed
- Indentation is now obtained via string_view. Users should see minor codegen performance
improvement
- Module instance indentation logic is changed. No visible change to the users.

Fixed
- Slice detection in port decoupling is now fixed.

Added
- Add clk_en cast

Changed
- vars are now packed by default in C++

Fixed
- Fix pyast logic with python3.9+
- fix port decuople logic that moves wire connection inside a stmt block
- Fix a bug where var cast won't pass sources to parent

Fixed
- Fix consteval corner cases

Added
- Python3.9 support