Kratos

Added
- Allow top name to be changed when converting generator to magma circuit
- Add ability to output `BTOR2` via `yosys`. Notice that some of the semantics needs sv2v's conversion.
- Add support for `for` loops that can be converted into SystemVerilog `for` loops.
This is only enabled when the generator is not in debug mode.
- Add `resize` function and resize as a new variable cast
- Add a pass to check top-level `if` statement in `always_comb` to make sure
variables are inferred as D flip-flops in DC (145.
- Add struct extract pass for `VarPacked`.

Changed
- Refactor C++ core interfaces: `generator()` and `const` usage in simulator.
This should not affect Python front end
- All Travis tests are moved to Github Actions.
- Refactor `debug` to `debug_fn_ln` flag in `verilog` function.
- Speed up CI builds by turning on debug mode (144).

Fixed
- Use generated name when storing generator variables
- Fix a bug where the top module is not in debug mode but child is during debug info dump

Added
- add bulking wiring when adding a child instance in python wrapper
- Add sanity check on width 0
- Add dedicated docker image for kratos testing
- Add source-level coverage report in xml cobertura format
- ncsim
- verilator
- Add insert verilator info to verilog function
- Add support for block comment in Python, which will turn into a normal comment stmt

Changed
- Relax output port inline requirements
- Code base refactoring based on clang-tidy-9
- All C++ unit tests tested against valgrind
- Use to_string() instead of name when throwing an exception
- merge_if_block is off by default and need to turn on by an attribute
- Allow sequence-based property to be inserted into normal design
- util.py helper functions now support single arguments

Fixed
- Fix nested fsm next state inferred as latch (95)
- Fix a bug where explicit array is not passed down to the wrapper
- Fix bit select on logic
- Fix nested loop in pyast
- Fix line number tracking when merging code in Python side
- Fix a bug in the simulator where default case will hit seg-fault
- Fix array flattening logic when dumping debug database
- Fix [n, 1] slicing where the last dim is 1

Fixed
- Fix multi-driver algorithm again

Added
- Add logical operator, i.e. && and ||
- Add direct python code transform from short-circuited boolean ops to proper function calls
- Add additional support for passes in Python. Improve Attribute creation

Fixed
- Fix the bug in nested var slice; the VarSlice class tried to walk the chain back, which is wrong
- Fix a multi-driver bug where you can have priority assignment in an combinational block

Changed
- Refactor get tokens in C++

Added
- Add full docker build image ready for ncsim and verilator
- Add coverage report from both C++ and python code
- Expose more C++ to Python

Changed
- Refactor get tokens in C++

Added
- Add a pass to extract all variable information
- Add spectrum-based fault analyser
- Add docker release for latest master build

Changed
- Adjust `pybind11` remote.

Fixed
- Fix a bug where a sliced vars is added as source instead of
sink