Kratos

Added
- Add `unwire` function to generator

Changed
- Skip driver test if the variable is sliced by another variable
- Change python requirements to >= 3.6 since 3.5 is EOL

Fixed
- Fix resizing on iter variable
- Fix clone port width calculation

Added
- Added packed struct array
- Allow parameters to be "type", advanced use only
- Enhance copy port definition by copying parameter as well
- Add enum, struct, and raw_type to copy port definition
- Allow parameter setting in add_child function
- Add `__len__` to var, which has the same semantics as array size in Python
- Add multi-stage generation support. The context will keep track of already generated instances
- Allow additoinal frames for fn_ln inspection
- Add tests to run on examples
- Add ability to resize parameter at compile time (159)
- Add support for parameter as variable width
- Add builtin tasks support, e.g., $clog2


Changed
- Parameter value codegen is adjusted based on initial value
- case statement will have begin-end block if the single statement is not an assignment

Fixed
- Fix var_width for packed struct (157)
- Fix typo in ast (158)
- Fix cerr printout using mutex lock
- Fix parameter propagation when flattening the instances
- Fix slice on parametrization with width
- Fix error message in interface valid varible name

Added
- Add helper functions to get connected ports
- Add async reset cast
- Add ability to specify parameter value when adding child generator
- Add iter support in port/var/param proxy (Python)
- Add parameter initial value
- Allow port types to be change during runtime in Python
- Add port creation with another port's definition in Python
- Add uart examples
- Add support for raw package import and raw parameter type
- Add helper function to tell if the port is connected or not
- Allow variable size to be parametrized by param
- Add pow op

Changed
- Relax if to case restrictions
- Adjust param codegen
- Sort port by directions as well (grouping inputs and outputs)

Fixed
- Fix stdfs linking if filesystem not found
- Fix complex expression with const generator
- Fix type in sram generator (150)
- Fix value update in param chaining

Added
- More SVA actions, such as `cover`
- Add `src` attribute for yosys code generation

Changed
- Simplified FSM code generation
- Disable parallel module instantiation

Fixed
- Fix stmt access in passes, which may cause memory access error

Added
- A pass to automatically insert clock gating logic into the design
- A pass to automatically insert synchronous reset based on async reset logic
- Add helper function in Python to construct clock enable ports and type conversion
- Add port and var parametrized by array size as a Verilog Parameter
- Add statement clone logic
- Move scope eval to each ast transformer (148)
- Add a switch to force loop unroll in python add_always
- Add find_attribute to simplify the attribute search

Changed
- Refactor clear source and clear sinks so that the statements will be removed from parent

Fixed
- Fix enum const generator assignment parent generated from FSM
- Fix a bug where the for loop may not be generated correctly

Added
- `always_latch` code generation and Python front-end
- Parametrized always blocks as function arguments (as kwargs)
- Allow slicing being used in the if condition in pyast

Changed
- Update `to_magma` logic due to upstream changes in magma IO
- Refactor string join namespace

Fixed
- Keep packed attribute when creating new expressions
- Fix a loop construction bug where a bit signal cannot be sliced
- Fix var casted as ports
- Fix move link with self loop
- Fix error message in add child generator