Added
- SystemVerilog interface support (123)
- Better integration ability to other Python-based generators
- Allow `enum` on port (public enum definition); 122
- Add context variables to `If` statement
Changed
- Pause on clock not enabled by default
- Reduce verbosity in enum creation; sort enum by values, not by name
- Automatically detect `<filesystem>` availability
- Merge static elaboration passes with `for` and `if`.
Fixed
- Numerous simulator issue fixes
- Fixed a known problem with astor-based code gen where long statement causes error (125)