(Breaking change) - Method rename: types.axi.AxiMemoryModel.memory_word_length() -> types.axi.AxiMemoryModel.shape_to_memory_size() - Some memory access methods of AxiMemoryModel, such as "set_memory()", uses the bit-level alignment instead of the word-level alignment in the previous version.
Test environment ====
1.1.0
Update ====
- Big update of Veriloggen.Thread and Stream - (Breaking change) No python 2.x support
Test environment ====
1.0.5
Update ====
- More general operator name aliases, such as Add, Sub, Mul, and Div, are added.
Test environment ====
1.0.4
Update ====
- Submodule functionality is improved. Parameter and localparams can be correctly handled in a parent module. - Read/Write dataflow behavior of RAM is update. Sign options of some data-related signals are changed to 'signed=True', so that negative values can can be handled correctly. - AxiMemoryModel supports read/write methods to access the register array of the model from the simulation thread.
Test environment ====
1.0.3
Update ====
- veriloggen.types.ipcore is updated for the latest IPgen.
Test environment ====
1.0.2
Update ====
- veriloggen.thread.Stream: read_parameter(obj, size, point=0, signed=True) is a stream generator from a parameter register.