Veriloggen

Update
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- Default sign of dataflow operators is changed to 'signed' from 'unsigned'.


Test environment
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Update
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- This is a first major release. This version includes numerous big updates of all components from the previous version.


Test environment
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Update
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Fixed-point supports in veriloggen.thread are implemented.


Test environment
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Update
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- "Submodule" is implemented. Now you can create an instance of submodule very easily.

Test environment
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Update
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A portable IP-core synthesis is now supported. You can easily create an original IP-core just by writing Python!

- AXI-slave interface and memory-mapped register are supported
- AXI-master in veriloggen.thread supports read/write method to access to a memory-mapped register easily
- AXI4/Avalon IP-core packager support via IPgen is added
- Synopsys VCS (very fast commercial Verilog simulator) support is added

Test environment
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This is the first version that includes veriloggen.thread, a tightly-coupled high-level synthesis compiler embedded within Veriloggen HDL.

veriloggen.thread

- Tightly-coupled high-level synthesis compiler emedded within Veriloggen HDL.
- This compiler supports tightly-coupled interaction between RTL definitions by Veriloggen HDL, embedding RTL definitions in HLS definitions (intrinsic), and concurrent multithreading.
- Additionally, this supports the stream processing via veriloggen.dataflow for high performance processing.
- Please see veriloggen/tests/extensions/threads_/ and veriloggen/examples/ to find many examples.