Veriloggen

Update
====

- Updated FSM extensions.

Test environment
====

macOS 11.4 (Apple Silicon M1)
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- Python 3.9.5
- Icarus Verilog 11.0
- Pyverilog 1.3.0
- numpy: 1.20.3

Ubuntu 20.04.2 (AMD Ryzen 9 5950X)
---

- Python 3.7.7 / 3.9.5
- Icarus Verilog 10.3
- Pyverilog 1.3.0
- numpy: 1.20.3

Update
====

Thread
---

- Introducing User-friendly compilation error messages.
- Removing `global` and `nonlocal` supports.

Stream
---

- Added `CustomCounter`, which takes an update rule function of counter values.
- Stream can read/write a FIFO by `read_fifo` and `write_fifo`, as well as `read_RAM` and `write_RAM`.
- Address generator function can be used with Stream by `set_source_generator` and `set_sink_generator`.
- Updated the divider.

Test environment
====

macOS 11.4 (Apple Silicon M1 / Intel Core i9)
----

- Python 3.9.5
- Icarus Verilog 11.0
- Pyverilog 1.3.0
- numpy: 1.20.3

Ubuntu 20.04.2 (AMD Ryzen 9 5950X)
---

- Python 3.7.7 / 3.9.5
- Icarus Verilog 10.3
- Pyverilog 1.3.0
- numpy: 1.20.3

Update
====

- (As well as 1.8.9) Update of the counter and counting rule of outstanding write-data.

Test environment
====

macOS 11.3.1 (Apple Silicon M1)
----

- Python 3.9.4
- Icarus Verilog 11.0
- Pyverilog 1.3.0
- numpy: 1.20.2

macOS 11.3.1 (Intel Core i9)
----

- Python 3.9.4
- Icarus Verilog 11.0
- Pyverilog 1.3.0
- numpy: 1.20.2

Ubuntu 20.04.2 (AMD Ryzen 9 5950X)
---

- Python 3.7.7 / 3.9.4
- Icarus Verilog 10.3
- Pyverilog 1.3.0
- numpy: 1.20.2

Update
====

- A bug fix of data transfer mechanism on AXI-Stream with vthread.FIFO.

Test environment
====

Update
====

- (as well as 1.8.8) A bug fix of the update rule of outstanding_wreq_count in types.axi.

Test environment
====

Update
====

- `split_read_write` method is added: The method splits an AXI port into two independent AXI ports for read and write respectively.

Test environment
====