Veriloggen

Update
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- Bug fix: Fixed a bug that a read/write request in AXI-slave interfaces can be dismissed.
- Updated Thread compiler (thread.compiler) for Python 3.9.

Test environment
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Update
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- AXI-Stream is supported.
- The implementation of stream.Counter is renewed, so that some bugs of stream.Counter are fixed.
- stream.Sync operator that synchronize explicitly the start stages of input variables is added.
- stream.ForwardDest and stream.ForwardSource for data forwarding between stream.read_RAM and stream.write_RAM is added. This operator is required to realize a read_modify_write_RAM operator.
- stream.Alias is added.
- stream.ReduceMax, ReduceMin, ReduceArgMax, and ReduceArgMin are added for NNgen.

Test environment
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Update
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- Some template text files for IP-XACT were not included in the tar file for PyPI in the previous version. This version include a bug fix such the files are included.
- README.rst was removed. Instead README.md is used for PyPI description.
- Memory image creation methods were optimized and accelerated by using numpy.

Test environment
====

Update
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- veriloggen.core: N-dimension array is supported for almost variable types.
- veriloggen.stream: Accumulator registers in stream pipelines are kept after executions for continuous sequent executions.
- veriloggen.types.axi: The bit-width of AxLOCK is changed to 1 according to the AXI4 specification.


Test environment
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Update
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- A bug fix of generate-scope handling in veriloggen.from_verilog and veriloggen.resolver.

Test environment
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Update
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- stream.ToExtern/FromExtern: External behavior definition in RTL.
- stream.Reg: External Reg that can be accessed from RTL/Thread.
- stream.ReadRAM/WriteRAM: Indirect RAM access interfaces
- Stream.source_join_and_run: fast handshake method for sequent join and re-run.

Test environment
====