Veriloggen

Update

This version includes some challenging updates of hardware interface abstractions.
- veriloggen.types: Abstractions of frequent-appeared interfaces, such as on-chip memory and on-chip bus, are implemented. Please see the test codes in "tests/extension/types_/".
- veriloggen.dataflow.DataflowManager is added: it manages dataflow variable implementations on an existing Module objects and automatically synthesizes native signal objects belonging to the Module.
- veriloggen.dataflow supports read/write operations from outside of dataflow definitions.
- veriloggen.FSM and Seq support more human-readable assignment definitions by the object call as a method. Please see the test codes in "tests/extension/fsm_/" and "tests/extension/seq_/".
- The feature of existing Verilog importation has been improved.
- Fundamental objects in veriloggen.core.types supports the bit_length() method to return its bit width.

Test environment

Mac OSX 10.11.6 (El Capitan)
- python 3.5.2
- python 2.7.12

Ubuntu 16.04 LTS
- python 3.5.2
- python 2.7.12

Update

Minor update:
- core/vtypes.py: argument order of vtypes objects are changed.
- verilog/to_verilog.py: a bug of blocking substitution is fixed.

Test environment

Update
- dataflow: dataflow-based high-level synthesis extension
- utils/fixed: fixed-point extension

Test environment

Update
- Multiple instance handling capability is improved.
- copy_params/copy_ports/connect_params/connect_ports support the prefix, postfix, and exclude options.

Test environment

Update
- Import path to the libraries have been changed.
- Dataflow has been renamed as Pipeline, because a new dataflow library is under development.
- Bugs of Pipeline (Dataflow) have been resolved.

Test environment

Update
- to_verilog and from_verilog: prettified code generation from imported original RTL.
- test scripts are added.

Test environment