Veriloggen

Update
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- Update of the counter and counting rule of outstanding write-data.

Test environment
====

macOS 11.3.1 (Apple Silicon M1)
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- Python 3.9.4
- Icarus Verilog 11.0
- Pyverilog 1.3.0
- numpy: 1.20.2

macOS 11.3.1 (Intel Core i9)
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- Python 3.9.4
- Icarus Verilog 11.0
- Pyverilog 1.3.0
- numpy: 1.20.2

Ubuntu 20.04.2 (AMD Ryzen 9 5950X)
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- Python 3.7.7 / 3.9.4
- Icarus Verilog 10.3
- Pyverilog 1.3.0
- numpy: 1.20.2

Update
====

- A bug fix of the update rule of outstanding_wreq_count in types.axi.

Test environment
====

Update
====

- `split_read_write` method is added: The method splits an AXI port into two independent AXI ports for read and write respectively.

Test environment
====

Update
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- Bug fix of AxiMultiportMemoryModel.

Test environment
====

Update
====

- Bug fix: `dma_wait` method is modified. `dma_wait` and `dma_wait_response` methods wait the write response (bvalid) from the corresponding slave interface.

Test environment
====

Update
====

- Bug fix: Fixed a bug that a one of simultaneous read/write requests can be dismissed in AXI-slave interface.

Test environment
====